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Commit dfbb37d2 authored by Alexander Beykun's avatar Alexander Beykun Committed by Gerrit - the friendly Code Review server
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drm/msm/dsi-staging: fix dsi clock voting for dsi-1 only panel



Current design treats clock controller index as an index of clock
configuration inside clock manager structure. For dsi-1 only case
controller index is 1, but clock configuration is stored at index 0.
Patch adds mapping inside clock manager to match dsi controller
indexes with correct core and link clock configurations.

Change-Id: Ie3a467d87f81d9f0b085cc0ab6156c65b5bb8e27
Signed-off-by: default avatarAlexander Beykun <abeykun@codeaurora.org>
parent 68ad8c92
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+17 −0
Original line number Diff line number Diff line
@@ -151,11 +151,28 @@ typedef int (*pre_clockon_cb)(void *priv,
			      enum dsi_clk_state new_state);


/**
 * struct dsi_clk_info - clock information for DSI hardware.
 * @name:                    client name.
 * @c_clks[MAX_DSI_CTRL]     array of core clock configurations
 * @l_clks[MAX_DSI_CTRL]     array of link clock configurations
 * @bus_handle[MAX_DSI_CTRL] array of bus handles
 * @ctrl_index[MAX_DSI_CTRL] array of DSI controller indexes mapped
 *                           to core and link clock configurations
 * @pre_clkoff_cb            callback before clock is turned off
 * @post_clkoff_cb           callback after clock is turned off
 * @post_clkon_cb            callback after clock is turned on
 * @pre_clkon_cb             callback before clock is turned on
 * @priv_data                pointer to private data
 * @master_ndx               master DSI controller index
 * @dsi_ctrl_count           number of DSI controllers
 */
struct dsi_clk_info {
	char name[MAX_STRING_LEN];
	struct dsi_core_clk_info c_clks[MAX_DSI_CTRL];
	struct dsi_link_clk_info l_clks[MAX_DSI_CTRL];
	u32 bus_handle[MAX_DSI_CTRL];
	u32 ctrl_index[MAX_DSI_CTRL];
	pre_clockoff_cb pre_clkoff_cb;
	post_clockoff_cb post_clkoff_cb;
	post_clockon_cb post_clkon_cb;
+27 −2
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@ struct dsi_clk_mngr {
	u32 master_ndx;
	struct dsi_core_clks core_clks[MAX_DSI_CTRL];
	struct dsi_link_clks link_clks[MAX_DSI_CTRL];
	u32 ctrl_index[MAX_DSI_CTRL];
	u32 core_clk_state;
	u32 link_clk_state;

@@ -58,6 +59,22 @@ struct dsi_clk_client_info {
	struct dsi_clk_mngr *mngr;
};

static int _get_clk_mngr_index(struct dsi_clk_mngr *mngr,
				u32 dsi_ctrl_index,
				u32 *clk_mngr_index)
{
	int i;

	for (i = 0; i < mngr->dsi_ctrl_count; i++) {
		if (mngr->ctrl_index[i] == dsi_ctrl_index) {
			*clk_mngr_index = i;
			return 0;
		}
	}

	return -EINVAL;
}

/**
 * dsi_clk_set_link_frequencies() - set frequencies for link clks
 * @clks:         Link clock information
@@ -70,7 +87,7 @@ struct dsi_clk_client_info {
int dsi_clk_set_link_frequencies(void *client, struct link_clk_freq freq,
				u32 index)
{
	int rc = 0;
	int rc = 0, clk_mngr_index = 0;
	struct dsi_clk_client_info *c = client;
	struct dsi_clk_mngr *mngr;

@@ -80,8 +97,15 @@ int dsi_clk_set_link_frequencies(void *client, struct link_clk_freq freq,
	}

	mngr = c->mngr;
	memcpy(&mngr->link_clks[index].freq, &freq,
	rc = _get_clk_mngr_index(mngr, index, &clk_mngr_index);
	if (rc) {
		pr_err("failed to map control index %d\n", index);
		return -EINVAL;
	}

	memcpy(&mngr->link_clks[clk_mngr_index].freq, &freq,
		sizeof(struct link_clk_freq));

	return rc;
}

@@ -1084,6 +1108,7 @@ void *dsi_display_clk_mngr_register(struct dsi_clk_info *info)
		memcpy(&mngr->link_clks[i].clks, &info->l_clks[i],
			sizeof(struct dsi_link_clk_info));
		mngr->core_clks[i].bus_handle = info->bus_handle[i];
		mngr->ctrl_index[i] = info->ctrl_index[i];
	}

	INIT_LIST_HEAD(&mngr->client_list);
+1 −0
Original line number Diff line number Diff line
@@ -2282,6 +2282,7 @@ static int dsi_display_bind(struct device *dev,
			sizeof(struct dsi_link_clk_info));
		info.bus_handle[i] =
			display_ctrl->ctrl->axi_bus_info.bus_handle;
		info.ctrl_index[i] = display_ctrl->ctrl->index;
	}

	info.pre_clkoff_cb = dsi_pre_clkoff_cb;