Loading arch/mips/kernel/smp.c +4 −21 Original line number Original line Diff line number Diff line Loading @@ -51,31 +51,14 @@ int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */ EXPORT_SYMBOL(phys_cpu_present_map); EXPORT_SYMBOL(phys_cpu_present_map); EXPORT_SYMBOL(cpu_online_map); EXPORT_SYMBOL(cpu_online_map); /* This happens early in bootup, can't really do it better */ static void smp_tune_scheduling (void) static void smp_tune_scheduling (void) { { struct cache_desc *cd = ¤t_cpu_data.scache; struct cache_desc *cd = ¤t_cpu_data.scache; unsigned long cachesize; /* kB */ unsigned long cachesize = cd->linesz * cd->sets * cd->ways; unsigned long cpu_khz; /* if (cachesize > max_cache_size) * Crude estimate until we actually meassure ... max_cache_size = cachesize; */ cpu_khz = loops_per_jiffy * 2 * HZ / 1000; /* * Rough estimation for SMP scheduling, this is the number of * cycles it takes for a fully memory-limited process to flush * the SMP-local cache. * * (For a P5 this pretty much means we will choose another idle * CPU almost always at wakeup time (this is due to the small * L1 cache), on PIIs it's around 50-100 usecs, depending on * the cache size) */ if (!cpu_khz) return; cachesize = cd->linesz * cd->sets * cd->ways; } } extern void __init calibrate_delay(void); extern void __init calibrate_delay(void); Loading Loading
arch/mips/kernel/smp.c +4 −21 Original line number Original line Diff line number Diff line Loading @@ -51,31 +51,14 @@ int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */ EXPORT_SYMBOL(phys_cpu_present_map); EXPORT_SYMBOL(phys_cpu_present_map); EXPORT_SYMBOL(cpu_online_map); EXPORT_SYMBOL(cpu_online_map); /* This happens early in bootup, can't really do it better */ static void smp_tune_scheduling (void) static void smp_tune_scheduling (void) { { struct cache_desc *cd = ¤t_cpu_data.scache; struct cache_desc *cd = ¤t_cpu_data.scache; unsigned long cachesize; /* kB */ unsigned long cachesize = cd->linesz * cd->sets * cd->ways; unsigned long cpu_khz; /* if (cachesize > max_cache_size) * Crude estimate until we actually meassure ... max_cache_size = cachesize; */ cpu_khz = loops_per_jiffy * 2 * HZ / 1000; /* * Rough estimation for SMP scheduling, this is the number of * cycles it takes for a fully memory-limited process to flush * the SMP-local cache. * * (For a P5 this pretty much means we will choose another idle * CPU almost always at wakeup time (this is due to the small * L1 cache), on PIIs it's around 50-100 usecs, depending on * the cache size) */ if (!cpu_khz) return; cachesize = cd->linesz * cd->sets * cd->ways; } } extern void __init calibrate_delay(void); extern void __init calibrate_delay(void); Loading