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Commit de6b0345 authored by Chris Zankel's avatar Chris Zankel
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[XTENSA] Add volatile keyword to asm statements accessing counter registers 



The compiler get's sometimes to smart and doesn't reread the
counter registers and the kernel doesn't schedule until the
counter wraps around.

Signed-off-by: default avatarChris Zankel <chris@zankel.net>
parent 03dfa442

include/asm-xtensa/timex.h

+4 −4
Original line number Diff line number Diff line
@@ -63,10 +63,10 @@ extern cycles_t cacheflush_time; 
 * Register access.

 */



#define WSR_CCOUNT(r)	  __asm__("wsr %0,"__stringify(CCOUNT) :: "a" (r))

#define RSR_CCOUNT(r)	  __asm__("rsr %0,"__stringify(CCOUNT) : "=a" (r))

#define WSR_CCOMPARE(x,r) __asm__("wsr %0,"__stringify(CCOMPARE)"+"__stringify(x) :: "a"(r))

#define RSR_CCOMPARE(x,r) __asm__("rsr %0,"__stringify(CCOMPARE)"+"__stringify(x) : "=a"(r))

#define WSR_CCOUNT(r)	  asm volatile ("wsr %0,"__stringify(CCOUNT) :: "a" (r))

#define RSR_CCOUNT(r)	  asm volatile ("rsr %0,"__stringify(CCOUNT) : "=a" (r))

#define WSR_CCOMPARE(x,r) asm volatile ("wsr %0,"__stringify(CCOMPARE)"+"__stringify(x) :: "a"(r))

#define RSR_CCOMPARE(x,r) asm volatile ("rsr %0,"__stringify(CCOMPARE)"+"__stringify(x) : "=a"(r))



static inline unsigned long get_ccount (void)

{