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Commit de5a1217 authored by Channagoud Kadabi's avatar Channagoud Kadabi
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pinctrl: qcom: Add sdmbat pinctrl driver 



Add initial sdmbat driver to support pin configuration with
pinctrl framework for msmskunk

Change-Id: Ifa47b3f27af7a0087de1806fdc066c6ba3c5f22c
Signed-off-by: default avatarChannagoud Kadabi <ckadabi@codeaurora.org>
parent 53c1534d

Documentation/devicetree/bindings/pinctrl/qcom,sdmbat-pinctrl

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Qualcomm Technologies, Inc. SDMBAT TLMM block



This binding describes the Top Level Mode Multiplexer block found in the

SDMBAT platform.



- compatible:

	Usage: required

	Value type: <string>

	Definition: must be "qcom,sdmbat-pinctrl"



- reg:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: the base address and size of the TLMM register space.



- interrupts:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: should specify the TLMM summary IRQ.



- interrupt-controller:

	Usage: required

	Value type: <none>

	Definition: identifies this node as an interrupt controller



- #interrupt-cells:

	Usage: required

	Value type: <u32>

	Definition: must be 2. Specifying the pin number and flags, as defined

		    in <dt-bindings/interrupt-controller/irq.h>



- gpio-controller:

	Usage: required

	Value type: <none>

	Definition: identifies this node as a gpio controller



- #gpio-cells:

	Usage: required

	Value type: <u32>

	Definition: must be 2. Specifying the pin number and flags, as defined

		    in <dt-bindings/gpio/gpio.h>



Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for

a general description of GPIO and interrupt bindings.



Please refer to pinctrl-bindings.txt in this directory for details of the

common pinctrl bindings used by client devices, including the meaning of the

phrase "pin configuration node".



The pin configuration nodes act as a container for an arbitrary number of

subnodes. Each of these subnodes represents some desired configuration for a

pin, a group, or a list of pins or groups. This configuration can include the

mux function to select on those pin(s)/group(s), and various pin configuration

parameters, such as pull-up, drive strength, etc.





PIN CONFIGURATION NODES:



The name of each subnode is not important; all subnodes should be enumerated

and processed purely based on their content.



Each subnode only affects those parameters that are explicitly listed. In

other words, a subnode that lists a mux function but no pin configuration

parameters implies no information about any pin configuration parameters.

Similarly, a pin subnode that describes a pullup parameter implies no

information about e.g. the mux function.





The following generic properties as defined in pinctrl-bindings.txt are valid

to specify in a pin configuration subnode:



- pins:

	Usage: required

	Value type: <string-array>

	Definition: List of gpio pins affected by the properties specified in

		    this subnode.



		    Valid pins are:

		      gpio0-gpio149

		        Supports mux, bias and drive-strength



		      sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd,

		      sdc2_data sdc1_rclk

		        Supports bias and drive-strength



- function:

	Usage: required

	Value type: <string>

	Definition: Specify the alternative function to be configured for the

		    specified pins. Functions are only valid for gpio pins.

		    Valid values are:



		    qup0, qup9, qdss_cti, ddr_pxi0, ddr_bist, atest_tsens2,

		    vsense_trigger, atest_usb1, qup_l4, GP_PDM1, qup_l5,

		    mdp_vsync, qup_l6, wlan2_adc1, atest_usb11, ddr_pxi2,

		    edp_lcd, dbg_out, wlan2_adc0, atest_usb10, m_voc,

		    tsif1_sync, ddr_pxi3, cam_mclk, pll_bypassnl, qdss_gpio0,

		    pll_reset, qdss_gpio1, qdss_gpio2, qdss_gpio3, cci_i2c,

		    qup1, gpio



- bias-disable:

	Usage: optional

	Value type: <none>

	Definition: The specified pins should be configued as no pull.



- bias-pull-down:

	Usage: optional

	Value type: <none>

	Definition: The specified pins should be configued as pull down.



- bias-pull-up:

	Usage: optional

	Value type: <none>

	Definition: The specified pins should be configued as pull up.



- output-high:

	Usage: optional

	Value type: <none>

	Definition: The specified pins are configured in output mode, driven

		    high.

		    Not valid for sdc pins.



- output-low:

	Usage: optional

	Value type: <none>

	Definition: The specified pins are configured in output mode, driven

		    low.

		    Not valid for sdc pins.



- drive-strength:

	Usage: optional

	Value type: <u32>

	Definition: Selects the drive strength for the specified pins, in mA.

		    Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16



Example:



	tlmm: pinctrl@03800000 {

		compatible = "qcom,sdmbat-pinctrl";

		reg = <0x03800000 0xc00000>;

		interrupts = <0 208 0>;

		gpio-controller;

		#gpio-cells = <2>;

		interrupt-controller;

		#interrupt-cells = <2>;

	};

arch/arm64/boot/dts/qcom/sdmbat-cdp.dtsi

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/* Copyright (c) 2016, The Linux Foundation. All rights reserved.

/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -11,4 +11,4 @@ 
 */



#include "msmskunk-cdp.dtsi"

#include "sdmbat-pinctrl.dtsi"

arch/arm64/boot/dts/qcom/sdmbat-mtp.dtsi

+2 −2
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/* Copyright (c) 2016, The Linux Foundation. All rights reserved.

/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -11,4 +11,4 @@ 
 */



#include "msmskunk-mtp.dtsi"

#include "sdmbat-pinctrl.dtsi"

arch/arm64/boot/dts/qcom/sdmbat-pinctrl.dtsi

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/* Copyright (c) 2017, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



&soc {

	tlmm: pinctrl@03800000 {

		compatible = "qcom,sdmbat-pinctrl";

		reg = <0x03800000 0xc00000>;

		interrupts = <0 208 0>;

		gpio-controller;

		#gpio-cells = <2>;

		interrupt-controller;

		#interrupt-cells = <2>;

	};

};

drivers/pinctrl/qcom/Kconfig

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@@ -88,6 +88,15 @@ config PINCTRL_MSMSKUNK 
	  Qualcomm Technologies Inc TLMM block found on the Qualcomm

	  Technologies Inc MSMSKUNK platform.



config PINCTRL_SDMBAT

	tristate "Qualcomm Technologies Inc SDMBAT pin controller driver"

	depends on GPIOLIB && OF

	select PINCTRL_MSM

	help

	  This is the pinctrl, pinmux, pinconf and gpiolib driver for the

	  Qualcomm Technologies Inc TLMM block found on the Qualcomm

	  Technologies Inc SDMBAT platform.





config PINCTRL_MSM8996

	tristate "Qualcomm MSM8996 pin controller driver"