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Commit dd607d23 authored by Sergei Shtylyov's avatar Sergei Shtylyov Committed by Linus Torvalds
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[PATCH] sl82c105: straighten up IDE control/status register caching 



Straighten up the IDE control/status register caching -- you *really* can't
cache the shared register per-channel and hope that it won't get out ouf
sync.

Set the PIO fallback mode to PIO0 for the slave drive as well as master --
there was no point in having them different (most probably a resutl of
typo).

Do a bit of reformat and cleanup while at it...

Signed-off-by: default avatarSergei Shtylyov <sshtylyov@ru.mvista.com>
Acked-by: default avatarAlan Cox <alan@lxorguk.ukuu.org.uk>
Cc: Bartlomiej Zolnierkiewicz <B.Zolnierkiewicz@elka.pw.edu.pl>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent b10a0686

drivers/ide/pci/sl82c105.c

+13 −18
Original line number Original line Diff line number Diff line
@@ -299,14 +299,14 @@ static void sl82c105_selectproc(ide_drive_t *drive) 
	//DBG(("sl82c105_selectproc(drive:%s)\n", drive->name));

	//DBG(("sl82c105_selectproc(drive:%s)\n", drive->name));





	mask = hwif->channel ? CTRL_P1F16 : CTRL_P0F16;

	mask = hwif->channel ? CTRL_P1F16 : CTRL_P0F16;

	old = val = *((u32 *)&hwif->hwif_data);

	old = val = (u32)pci_get_drvdata(dev);

	if (drive->using_dma)

	if (drive->using_dma)

		val &= ~mask;

		val &= ~mask;

	else

	else

		val |= mask;

		val |= mask;

	if (old != val) {

	if (old != val) {

		pci_write_config_dword(dev, 0x40, val);	

		pci_write_config_dword(dev, 0x40, val);	

		*((u32 *)&hwif->hwif_data) = val;

		pci_set_drvdata(dev, (void *)val);

	}

	}

}

}
@@ -316,14 +316,13 @@ static void sl82c105_selectproc(ide_drive_t *drive) 
 */

 */

static void sl82c105_resetproc(ide_drive_t *drive)

static void sl82c105_resetproc(ide_drive_t *drive)

{

{

	ide_hwif_t *hwif = HWIF(drive);

	struct pci_dev *dev = HWIF(drive)->pci_dev;

	struct pci_dev *dev = hwif->pci_dev;

	u32 val;

	u32 val;





	DBG(("sl82c105_resetproc(drive:%s)\n", drive->name));

	DBG(("sl82c105_resetproc(drive:%s)\n", drive->name));





	pci_read_config_dword(dev, 0x40, &val);

	pci_read_config_dword(dev, 0x40, &val);

	*((u32 *)&hwif->hwif_data) = val;

	pci_set_drvdata(dev, (void *)val);

}

}

	

	

/*

/*
@@ -394,6 +393,7 @@ static unsigned int __devinit init_chipset_sl82c105(struct pci_dev *dev, const c 
	pci_read_config_dword(dev, 0x40, &val);

	pci_read_config_dword(dev, 0x40, &val);

	val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16;

	val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16;

	pci_write_config_dword(dev, 0x40, val);

	pci_write_config_dword(dev, 0x40, val);

	pci_set_drvdata(dev, (void *)val);





	return dev->irq;

	return dev->irq;

}

}
@@ -404,10 +404,8 @@ static unsigned int __devinit init_chipset_sl82c105(struct pci_dev *dev, const c 




static void __devinit init_hwif_sl82c105(ide_hwif_t *hwif)

static void __devinit init_hwif_sl82c105(ide_hwif_t *hwif)

{

{

	struct pci_dev *dev = hwif->pci_dev;

	unsigned int rev;

	unsigned int rev;

	u8 dma_state;

	u8 dma_state;

	u32 val;





	DBG(("init_hwif_sl82c105(hwif: ide%d)\n", hwif->index));

	DBG(("init_hwif_sl82c105(hwif: ide%d)\n", hwif->index));
@@ -415,19 +413,16 @@ static void __devinit init_hwif_sl82c105(ide_hwif_t *hwif) 
	hwif->selectproc = sl82c105_selectproc;

	hwif->selectproc = sl82c105_selectproc;

	hwif->resetproc = sl82c105_resetproc;

	hwif->resetproc = sl82c105_resetproc;





	/* Default to PIO 0 for fallback unless tuned otherwise,

	/*

	 * we always autotune PIO, this is done before DMA is

	 * Default to PIO 0 for fallback unless tuned otherwise.

	 * checked, so there is no risk of accidentally disabling

	 * We always autotune PIO,  this is done before DMA is checked,

	 * DMA

	 * so there's no risk of accidentally disabling DMA

	 */

	 */

	hwif->drives[0].pio_speed = XFER_PIO_0;

	hwif->drives[0].pio_speed = XFER_PIO_0;

	hwif->drives[0].autotune = 1;

	hwif->drives[0].autotune = 1;

	hwif->drives[1].pio_speed = XFER_PIO_1;

	hwif->drives[1].pio_speed = XFER_PIO_0;

	hwif->drives[1].autotune = 1;

	hwif->drives[1].autotune = 1;





	pci_read_config_dword(dev, 0x40, &val);

	*((u32 *)&hwif->hwif_data) = val;

	

	hwif->atapi_dma = 0;

	hwif->atapi_dma = 0;

	hwif->mwdma_mask = 0;

	hwif->mwdma_mask = 0;

	hwif->swdma_mask = 0;

	hwif->swdma_mask = 0;