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Commit dd508ae2 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (36 commits)
  powerpc/gc/wii: Remove get_irq_desc()
  powerpc/gc/wii: hlwd-pic: convert irq_desc.lock to raw_spinlock
  powerpc/gamecube/wii: Fix off-by-one error in ugecon/usbgecko_udbg
  powerpc/mpic: Fix problem that affinity is not updated
  powerpc/mm: Fix stupid bug in subpge protection handling
  powerpc/iseries: use DECLARE_COMPLETION_ONSTACK for non-constant completion
  powerpc: Fix MSI support on U4 bridge PCIe slot
  powerpc: Handle VSX alignment faults correctly in little-endian mode
  powerpc/mm: Fix typo of cpumask_clear_cpu()
  powerpc/mm: Fix hash_utils_64.c compile errors with DEBUG enabled.
  powerpc: Convert BUG() to use unreachable()
  powerpc/pseries: Make declarations of cpu_hotplug_driver_lock() ANSI compatible.
  powerpc/pseries: Don't panic when H_PROD fails during cpu-online.
  powerpc/mm: Fix a WARN_ON() with CONFIG_DEBUG_PAGEALLOC and CONFIG_DEBUG_VM
  powerpc/defconfigs: Set HZ=100 on pseries and ppc64 defconfigs
  powerpc/defconfigs: Disable token ring in powerpc defconfigs
  powerpc/defconfigs: Reduce 64bit vmlinux by making acenic and cramfs modules
  powerpc/pseries: Select XICS and PCI_MSI PSERIES
  powerpc/85xx: Wrong variable returned on error
  powerpc/iseries: Convert to proc_fops
  ...
parents 7801edb0 95cd34b4
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+42 −0
Original line number Diff line number Diff line
* OpenPIC and its interrupt numbers on Freescale's e500/e600 cores

The OpenPIC specification does not specify which interrupt source has to
become which interrupt number. This is up to the software implementation
of the interrupt controller. The only requirement is that every
interrupt source has to have an unique interrupt number / vector number.
To accomplish this the current implementation assigns the number zero to
the first source, the number one to the second source and so on until
all interrupt sources have their unique number.
Usually the assigned vector number equals the interrupt number mentioned
in the documentation for a given core / CPU. This is however not true
for the e500 cores (MPC85XX CPUs) where the documentation distinguishes
between internal and external interrupt sources and starts counting at
zero for both of them.

So what to write for external interrupt source X or internal interrupt
source Y into the device tree? Here is an example:

The memory map for the interrupt controller in the MPC8544[0] shows,
that the first interrupt source starts at 0x5_0000 (PIC Register Address
Map-Interrupt Source Configuration Registers). This source becomes the
number zero therefore:
 External interrupt 0 = interrupt number 0
 External interrupt 1 = interrupt number 1
 External interrupt 2 = interrupt number 2
 ...
Every interrupt number allocates 0x20 bytes register space. So to get
its number it is sufficient to shift the lower 16bits to right by five.
So for the external interrupt 10 we have:
  0x0140 >> 5 = 10

After the external sources, the internal sources follow. The in core I2C
controller on the MPC8544 for instance has the internal source number
27. Oo obtain its interrupt number we take the lower 16bits of its memory
address (0x5_0560) and shift it right:
 0x0560 >> 5 = 43

Therefore the I2C device node for the MPC8544 CPU has to have the
interrupt number 43 specified in the device tree.

[0] MPC8544E PowerQUICCTM III, Integrated Host Processor Family Reference Manual
    MPC8544ERM Rev. 1 10/2007
+51 −1
Original line number Diff line number Diff line
@@ -108,12 +108,19 @@
		dcr-reg = <0x00c 0x002>;
	};

	MQ0: mq {
		compatible = "ibm,mq-440spe";
		dcr-reg = <0x040 0x020>;
	};

	plb {
		compatible = "ibm,plb-440spe", "ibm,plb-440gp", "ibm,plb4";
		#address-cells = <2>;
		#size-cells = <1>;
		/*        addr-child     addr-parent    size */
		ranges = <0x4 0xe0000000 0x4 0xe0000000 0x20000000
		ranges = <0x4 0x00100000 0x4 0x00100000 0x00001000
			  0x4 0x00200000 0x4 0x00200000 0x00000400
			  0x4 0xe0000000 0x4 0xe0000000 0x20000000
			  0xc 0x00000000 0xc 0x00000000 0x20000000
			  0xd 0x00000000 0xd 0x00000000 0x80000000
			  0xd 0x80000000 0xd 0x80000000 0x80000000
@@ -400,6 +407,49 @@
				0x0 0x0 0x0 0x3 &UIC3 0xa 0x4 /* swizzled int C */
				0x0 0x0 0x0 0x4 &UIC3 0xb 0x4 /* swizzled int D */>;
		};

		I2O: i2o@400100000 {
			compatible = "ibm,i2o-440spe";
			reg = <0x00000004 0x00100000 0x100>;
			dcr-reg = <0x060 0x020>;
		};

		DMA0: dma0@400100100 {
			compatible = "ibm,dma-440spe";
			cell-index = <0>;
			reg = <0x00000004 0x00100100 0x100>;
			dcr-reg = <0x060 0x020>;
			interrupt-parent = <&DMA0>;
			interrupts = <0 1>;
			#interrupt-cells = <1>;
			#address-cells = <0>;
			#size-cells = <0>;
			interrupt-map = <
				0 &UIC0 0x14 4
				1 &UIC1 0x16 4>;
		};

		DMA1: dma1@400100200 {
			compatible = "ibm,dma-440spe";
			cell-index = <1>;
			reg = <0x00000004 0x00100200 0x100>;
			dcr-reg = <0x060 0x020>;
			interrupt-parent = <&DMA1>;
			interrupts = <0 1>;
			#interrupt-cells = <1>;
			#address-cells = <0>;
			#size-cells = <0>;
			interrupt-map = <
				0 &UIC0 0x16 4
				1 &UIC1 0x16 4>;
		};

		xor-accel@400200000 {
			compatible = "amcc,xor-accelerator";
			reg = <0x00000004 0x00200000 0x400>;
			interrupt-parent = <&UIC1>;
			interrupts = <0x1f 4>;
		};
	};

	chosen {
+27 −0
Original line number Diff line number Diff line
@@ -204,6 +204,7 @@
			interrupt-parent = <&ipic>;
			tbi-handle = <&tbi0>;
			phy-handle = < &phy0 >;
			fsl,magic-packet;

			mdio@520 {
				#address-cells = <1>;
@@ -246,6 +247,7 @@
			interrupt-parent = <&ipic>;
			tbi-handle = <&tbi1>;
			phy-handle = < &phy1 >;
			fsl,magic-packet;

			mdio@520 {
				#address-cells = <1>;
@@ -309,6 +311,22 @@
			interrupt-parent = <&ipic>;
		};

		gtm1: timer@500 {
			compatible = "fsl,mpc8315-gtm", "fsl,gtm";
			reg = <0x500 0x100>;
			interrupts = <90 8 78 8 84 8 72 8>;
			interrupt-parent = <&ipic>;
			clock-frequency = <133333333>;
		};

		timer@600 {
			compatible = "fsl,mpc8315-gtm", "fsl,gtm";
			reg = <0x600 0x100>;
			interrupts = <91 8 79 8 85 8 73 8>;
			interrupt-parent = <&ipic>;
			clock-frequency = <133333333>;
		};

		/* IPIC
		 * interrupts cell = <intr #, sense>
		 * sense values match linux IORESOURCE_IRQ_* defines:
@@ -337,6 +355,15 @@
				      0x59 0x8>;
			interrupt-parent = < &ipic >;
		};

		pmc: power@b00 {
			compatible = "fsl,mpc8315-pmc", "fsl,mpc8313-pmc",
				     "fsl,mpc8349-pmc";
			reg = <0xb00 0x100 0xa00 0x100>;
			interrupts = <80 8>;
			interrupt-parent = <&ipic>;
			fsl,mpc8313-wakeup-timer = <&gtm1>;
		};
	};

	pci0: pci@e0008500 {
+81 −1
Original line number Diff line number Diff line
@@ -63,6 +63,24 @@
			reg = <0x200 0x100>;
		};

		gpio1: gpio-controller@c00 {
			#gpio-cells = <2>;
			compatible = "fsl,mpc8349-gpio";
			reg = <0xc00 0x100>;
			interrupts = <74 0x8>;
			interrupt-parent = <&ipic>;
			gpio-controller;
		};

		gpio2: gpio-controller@d00 {
			#gpio-cells = <2>;
			compatible = "fsl,mpc8349-gpio";
			reg = <0xd00 0x100>;
			interrupts = <75 0x8>;
			interrupt-parent = <&ipic>;
			gpio-controller;
		};

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
@@ -72,6 +90,12 @@
			interrupts = <14 0x8>;
			interrupt-parent = <&ipic>;
			dfsrr;

			eeprom: at24@50 {
				compatible = "st-micro,24c256";
				reg = <0x50>;
			};

		};

		i2c@3100 {
@@ -91,6 +115,25 @@
				interrupt-parent = <&ipic>;
			};

			pcf1: iexp@38 {
				#gpio-cells = <2>;
				compatible = "ti,pcf8574a";
				reg = <0x38>;
				gpio-controller;
			};

			pcf2: iexp@39 {
				#gpio-cells = <2>;
				compatible = "ti,pcf8574a";
				reg = <0x39>;
				gpio-controller;
			};

			spd: at24@51 {
				compatible = "at24,spd";
				reg = <0x51>;
			};

			mcu_pio: mcu@a {
				#gpio-cells = <2>;
				compatible = "fsl,mc9s08qg8-mpc8349emitx",
@@ -275,6 +318,24 @@
			reg = <0x700 0x100>;
			device_type = "ipic";
		};

		gpio-leds {
			compatible = "gpio-leds";

			green {
				label = "Green";
				gpios = <&pcf1 0 1>;
				linux,default-trigger = "heartbeat";
			};

			yellow {
				label = "Yellow";
				gpios = <&pcf1 1 1>;
				/* linux,default-trigger = "heartbeat"; */
				default-state = "on";
			};
		};

	};

	pci0: pci@e0008500 {
@@ -331,7 +392,26 @@
		compatible = "fsl,mpc8349e-localbus",
			     "fsl,pq2pro-localbus";
		reg = <0xe0005000 0xd8>;
		ranges = <0x3 0x0 0xf0000000 0x210>;
		ranges = <0x0 0x0 0xfe000000 0x1000000	/* flash */
			  0x1 0x0 0xf8000000 0x20000	/* VSC 7385 */
			  0x2 0x0 0xf9000000 0x200000	/* exp slot */
			  0x3 0x0 0xf0000000 0x210>;	/* CF slot */

		flash@0,0 {
			compatible = "cfi-flash";
			reg = <0x0      0x0 0x800000>;
			bank-width = <2>;
			device-width = <1>;
		};

		flash@0,800000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "cfi-flash";
			reg = <0x0 0x800000 0x800000>;
			bank-width = <2>;
			device-width = <1>;
		};

		pata@3,0 {
			compatible = "fsl,mpc8349emitx-pata", "ata-generic";
+1 −1
Original line number Diff line number Diff line
@@ -146,7 +146,7 @@

				fpga@2,4000 {
					compatible = "pika,fpga-sd";
					reg = <0x00000002 0x00004000 0x00000A00>;
					reg = <0x00000002 0x00004000 0x00004000>;
				};

				nor@0,0 {
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