Commit dc807347 authored Feb 20, 2017 by Lynus Vaz Committed by Gerrit - the friendly Code Review server Mar 16, 2017

msm: kgsl: Correct the register address in protected mode



On A6XX the CP protected mode status register contains the register
offset, and not the byte address. No further shifting is necessary to
convert it.

Change-Id: If8ab71386f213fef4561a9afb04af447e3360702
Signed-off-by: Lynus Vaz <lvaz@codeaurora.org>

parent 900cea2a

drivers/gpu/msm/adreno_a6xx.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -553,7 +553,7 @@ static void a6xx_cp_hw_err_callback(struct adreno_device *adreno_dev, int bit)
		KGSL_DRV_CRIT_RATELIMIT(device,
		"CP \| Protected mode error \| %s \| addr=%x \| status=%x\n",
		status2 & (1 << 20) ? "READ" : "WRITE",
		(status2 & 0x3FFFF) >> 2, status2);
		status2 & 0x3FFFF, status2);
		}
		if (status1 & BIT(A6XX_CP_AHB_ERROR))
		KGSL_DRV_CRIT_RATELIMIT(device,