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Commit dc65c97b authored by Aravind Venkateswaran's avatar Aravind Venkateswaran Committed by Gerrit - the friendly Code Review server
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msm: clk: qcom: fix recalc rate callback for 10nm DSI PLL 



Recalculate the DSI PLL VCO clock rate from the registers only
for the handoff usecases. This is due to the fact that the rate
calculation requires the knowledge of PLL out_div divider clock
rate which is only set after the VCO rate is set. This will
ensure that stale values are not used in VCO rate recalculation.

Change-Id: I690fba18ba59b9912c0bfe7284bfed793fd04cd3
Signed-off-by: default avatarAravind Venkateswaran <aravindh@codeaurora.org>
parent 8725a0c5

drivers/clk/qcom/mdss/mdss-dsi-pll-10nm.c

+13 −0
Original line number Diff line number Diff line
@@ -814,6 +814,19 @@ static unsigned long vco_10nm_recalc_rate(struct clk_hw *hw, 
	if (!vco->priv)

		pr_err("vco priv is null\n");



	/*

	 * Calculate the vco rate from HW registers only for handoff cases.

	 * For other cases where a vco_10nm_set_rate() has already been

	 * called, just return the rate that was set earlier. This is due

	 * to the fact that recalculating VCO rate requires us to read the

	 * correct value of the pll_out_div divider clock, which is only set

	 * afterwards.

	 */

	if (pll->vco_current_rate != 0) {

		pr_debug("returning vco rate = %lld\n", pll->vco_current_rate);

		return pll->vco_current_rate;

	}



	rc = mdss_pll_resource_enable(pll, true);

	if (rc) {

		pr_err("failed to enable pll(%d) resource, rc=%d\n",