Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit dc50ba7f authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon/kms: add dpm support for evergreen (v4) 



This adds dpm support for evergreen asics.  This includes:
- clockgating
- dynamic engine clock scaling
- dynamic memory clock scaling
- dynamic voltage scaling
- dynamic pcie gen1/gen2 switching (requires additional acpi support)

Set radeon.dpm=1 to enable.

v2: reduce stack usage, rename ulv struct
v3: fix thermal interrupt check notices by Jerome
v4: fix state enable

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 66229b20

drivers/gpu/drm/radeon/Makefile

+1 −1
Original line number Original line Diff line number Diff line
@@ -78,7 +78,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \ 
	atombios_encoders.o radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o \

	atombios_encoders.o radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o \

	si_blit_shaders.o radeon_prime.o radeon_uvd.o cik.o cik_blit_shaders.o \

	si_blit_shaders.o radeon_prime.o radeon_uvd.o cik.o cik_blit_shaders.o \

	r600_dpm.o rs780_dpm.o rv6xx_dpm.o rv770_dpm.o rv730_dpm.o rv740_dpm.o \

	r600_dpm.o rs780_dpm.o rv6xx_dpm.o rv770_dpm.o rv730_dpm.o rv740_dpm.o \

	rv770_smc.o

	rv770_smc.o cypress_dpm.o





radeon-$(CONFIG_COMPAT) += radeon_ioc32.o

radeon-$(CONFIG_COMPAT) += radeon_ioc32.o

radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o

radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o

drivers/gpu/drm/radeon/cypress_dpm.c

0 → 100644
+2105 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/radeon/cypress_dpm.h

0 → 100644
+134 −0
Original line number Original line Diff line number Diff line 
/*

 * Copyright 2011 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */

#ifndef __CYPRESS_DPM_H__

#define __CYPRESS_DPM_H__



#include "rv770_dpm.h"

#include "evergreen_smc.h"



struct evergreen_mc_reg_entry {

	u32 mclk_max;

	u32 mc_data[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE];

};



struct evergreen_mc_reg_table {

	u8 last;

	u8 num_entries;

	u16 valid_flag;

	struct evergreen_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];

	SMC_Evergreen_MCRegisterAddress mc_reg_address[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE];

};



struct evergreen_ulv_param {

	bool supported;

	struct rv7xx_pl *pl;

};



struct evergreen_arb_registers {

	u32 mc_arb_dram_timing;

	u32 mc_arb_dram_timing2;

	u32 mc_arb_rfsh_rate;

	u32 mc_arb_burst_time;

};



struct evergreen_power_info {

	/* must be first! */

	struct rv7xx_power_info rv7xx;

	/* flags */

	bool vddci_control;

	bool dynamic_ac_timing;

	bool abm;

	bool mcls;

	bool light_sleep;

	bool memory_transition;

	bool pcie_performance_request;

	bool pcie_performance_request_registered;

	bool sclk_deep_sleep;

	bool dll_default_on;

	bool ls_clock_gating;

	/* stored values */

	u16 acpi_vddci;

	u8 mvdd_high_index;

	u8 mvdd_low_index;

	u32 mclk_edc_wr_enable_threshold;

	struct evergreen_mc_reg_table mc_reg_table;

	struct atom_voltage_table vddc_voltage_table;

	struct atom_voltage_table vddci_voltage_table;

	struct evergreen_arb_registers bootup_arb_registers;

	struct evergreen_ulv_param ulv;

	/* smc offsets */

	u16 mc_reg_table_start;

};



#define CYPRESS_HASI_DFLT                               400000

#define CYPRESS_MGCGTTLOCAL0_DFLT                       0x00000000

#define CYPRESS_MGCGTTLOCAL1_DFLT                       0x00000000

#define CYPRESS_MGCGTTLOCAL2_DFLT                       0x00000000

#define CYPRESS_MGCGTTLOCAL3_DFLT                       0x00000000

#define CYPRESS_MGCGCGTSSMCTRL_DFLT                     0x81944bc0

#define REDWOOD_MGCGCGTSSMCTRL_DFLT                     0x6e944040

#define CEDAR_MGCGCGTSSMCTRL_DFLT                       0x46944040

#define CYPRESS_VRC_DFLT                                0xC00033



#define PCIE_PERF_REQ_REMOVE_REGISTRY   0

#define PCIE_PERF_REQ_FORCE_LOWPOWER    1

#define PCIE_PERF_REQ_PECI_GEN1         2

#define PCIE_PERF_REQ_PECI_GEN2         3

#define PCIE_PERF_REQ_PECI_GEN3         4



int cypress_convert_power_level_to_smc(struct radeon_device *rdev,

				       struct rv7xx_pl *pl,

				       RV770_SMC_HW_PERFORMANCE_LEVEL *level,

				       u8 watermark_level);

int cypress_populate_smc_acpi_state(struct radeon_device *rdev,

				    RV770_SMC_STATETABLE *table);

int cypress_populate_smc_voltage_tables(struct radeon_device *rdev,

					RV770_SMC_STATETABLE *table);

int cypress_populate_smc_initial_state(struct radeon_device *rdev,

				       struct radeon_ps *radeon_initial_state,

				       RV770_SMC_STATETABLE *table);

u32 cypress_calculate_burst_time(struct radeon_device *rdev,

				 u32 engine_clock, u32 memory_clock);

void cypress_notify_link_speed_change_before_state_change(struct radeon_device *rdev);

int cypress_upload_sw_state(struct radeon_device *rdev);

int cypress_upload_mc_reg_table(struct radeon_device *rdev);

void cypress_program_memory_timing_parameters(struct radeon_device *rdev);

void cypress_notify_link_speed_change_after_state_change(struct radeon_device *rdev);

int cypress_construct_voltage_tables(struct radeon_device *rdev);

int cypress_get_mvdd_configuration(struct radeon_device *rdev);

void cypress_enable_spread_spectrum(struct radeon_device *rdev,

				    bool enable);

void cypress_enable_display_gap(struct radeon_device *rdev);

int cypress_get_table_locations(struct radeon_device *rdev);

int cypress_populate_mc_reg_table(struct radeon_device *rdev);

void cypress_program_response_times(struct radeon_device *rdev);

int cypress_notify_smc_display_change(struct radeon_device *rdev,

				      bool has_display);

void cypress_enable_sclk_control(struct radeon_device *rdev,

				 bool enable);

void cypress_enable_mclk_control(struct radeon_device *rdev,

				 bool enable);

void cypress_start_dpm(struct radeon_device *rdev);

void cypress_advertise_gen2_capability(struct radeon_device *rdev);



#endif

drivers/gpu/drm/radeon/evergreen.c

+22 −0
Original line number Original line Diff line number Diff line
@@ -4167,6 +4167,7 @@ int evergreen_irq_set(struct radeon_device *rdev) 
	u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;

	u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;

	u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0;

	u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0;

	u32 dma_cntl, dma_cntl1 = 0;

	u32 dma_cntl, dma_cntl1 = 0;

	u32 thermal_int = 0;





	if (!rdev->irq.installed) {

	if (!rdev->irq.installed) {

		WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");

		WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
@@ -4186,6 +4187,8 @@ int evergreen_irq_set(struct radeon_device *rdev) 
	hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;

	hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;

	hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;

	hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;

	hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;

	hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;

	thermal_int = RREG32(CG_THERMAL_INT) &

		~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);





	afmt1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;

	afmt1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;

	afmt2 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;

	afmt2 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
@@ -4231,6 +4234,11 @@ int evergreen_irq_set(struct radeon_device *rdev) 
		}

		}

	}

	}





	if (rdev->irq.dpm_thermal) {

		DRM_DEBUG("dpm thermal\n");

		thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;

	}



	if (rdev->irq.crtc_vblank_int[0] ||

	if (rdev->irq.crtc_vblank_int[0] ||

	    atomic_read(&rdev->irq.pflip[0])) {

	    atomic_read(&rdev->irq.pflip[0])) {

		DRM_DEBUG("evergreen_irq_set: vblank 0\n");

		DRM_DEBUG("evergreen_irq_set: vblank 0\n");
@@ -4352,6 +4360,7 @@ int evergreen_irq_set(struct radeon_device *rdev) 
	WREG32(DC_HPD4_INT_CONTROL, hpd4);

	WREG32(DC_HPD4_INT_CONTROL, hpd4);

	WREG32(DC_HPD5_INT_CONTROL, hpd5);

	WREG32(DC_HPD5_INT_CONTROL, hpd5);

	WREG32(DC_HPD6_INT_CONTROL, hpd6);

	WREG32(DC_HPD6_INT_CONTROL, hpd6);

	WREG32(CG_THERMAL_INT, thermal_int);





	WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, afmt1);

	WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, afmt1);

	WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, afmt2);

	WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, afmt2);
@@ -4543,6 +4552,7 @@ int evergreen_irq_process(struct radeon_device *rdev) 
	u32 ring_index;

	u32 ring_index;

	bool queue_hotplug = false;

	bool queue_hotplug = false;

	bool queue_hdmi = false;

	bool queue_hdmi = false;

	bool queue_thermal = false;





	if (!rdev->ih.enabled || rdev->shutdown)

	if (!rdev->ih.enabled || rdev->shutdown)

		return IRQ_NONE;

		return IRQ_NONE;
@@ -4864,6 +4874,16 @@ int evergreen_irq_process(struct radeon_device *rdev) 
			DRM_DEBUG("IH: DMA trap\n");

			DRM_DEBUG("IH: DMA trap\n");

			radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);

			radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);

			break;

			break;

		case 230: /* thermal low to high */

			DRM_DEBUG("IH: thermal low to high\n");

			rdev->pm.dpm.thermal.high_to_low = false;

			queue_thermal = true;

			break;

		case 231: /* thermal high to low */

			DRM_DEBUG("IH: thermal high to low\n");

			rdev->pm.dpm.thermal.high_to_low = true;

			queue_thermal = true;

			break;

		case 233: /* GUI IDLE */

		case 233: /* GUI IDLE */

			DRM_DEBUG("IH: GUI idle\n");

			DRM_DEBUG("IH: GUI idle\n");

			break;

			break;
@@ -4886,6 +4906,8 @@ int evergreen_irq_process(struct radeon_device *rdev) 
		schedule_work(&rdev->hotplug_work);

		schedule_work(&rdev->hotplug_work);

	if (queue_hdmi)

	if (queue_hdmi)

		schedule_work(&rdev->audio_work);

		schedule_work(&rdev->audio_work);

	if (queue_thermal && rdev->pm.dpm_enabled)

		schedule_work(&rdev->pm.dpm.thermal.work);

	rdev->ih.rptr = rptr;

	rdev->ih.rptr = rptr;

	WREG32(IH_RB_RPTR, rdev->ih.rptr);

	WREG32(IH_RB_RPTR, rdev->ih.rptr);

	atomic_set(&rdev->ih.lock, 0);

	atomic_set(&rdev->ih.lock, 0);

drivers/gpu/drm/radeon/evergreen_smc.h

0 → 100644
+67 −0
Original line number Original line Diff line number Diff line 
/*

 * Copyright 2011 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */

#ifndef __EVERGREEN_SMC_H__

#define __EVERGREEN_SMC_H__



#include "rv770_smc.h"



#pragma pack(push, 1)



#define SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE 16



struct SMC_Evergreen_MCRegisterAddress

{

    uint16_t s0;

    uint16_t s1;

};



typedef struct SMC_Evergreen_MCRegisterAddress SMC_Evergreen_MCRegisterAddress;





struct SMC_Evergreen_MCRegisterSet

{

    uint32_t value[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE];

};



typedef struct SMC_Evergreen_MCRegisterSet SMC_Evergreen_MCRegisterSet;



struct SMC_Evergreen_MCRegisters

{

    uint8_t                             last;

    uint8_t                             reserved[3];

    SMC_Evergreen_MCRegisterAddress     address[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE];

    SMC_Evergreen_MCRegisterSet         data[5];

};



typedef struct SMC_Evergreen_MCRegisters SMC_Evergreen_MCRegisters;



#define EVERGREEN_SMC_FIRMWARE_HEADER_LOCATION 0x100



#define EVERGREEN_SMC_FIRMWARE_HEADER_softRegisters   0x0

#define EVERGREEN_SMC_FIRMWARE_HEADER_stateTable      0xC

#define EVERGREEN_SMC_FIRMWARE_HEADER_mcRegisterTable 0x20





#pragma pack(pop)



#endif