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Commit dc00b6a0 authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915/psr: Implement PSR2 w/a for gen9 



Found this while browsing Bspec. Looks like it applies to both skl and
kbl.

v2: Also for bxt (Art).

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Sonika Jindal <sonika.jindal@intel.com>
Cc: Durgadoss R <durgadoss.r@intel.com>
Cc: "Pandiyan, Dhinakaran" <dhinakaran.pandiyan@intel.com>
Cc: "Runyan, Arthur J" <arthur.j.runyan@intel.com>
Reviewed-by: default avatarSonika <Jindal&lt;sonika.jindal@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1463642060-30728-1-git-send-email-daniel.vetter@ffwll.ch
parent d4dcbdce

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -6033,6 +6033,7 @@ enum skl_disp_power_wells { 
#define CHICKEN_PAR1_1		_MMIO(0x42080)

#define  DPA_MASK_VBLANK_SRD	(1 << 15)

#define  FORCE_ARB_IDLE_PLANES	(1 << 14)

#define  SKL_EDP_PSR_FIX_RDWRAP	(1 << 3)



#define _CHICKEN_PIPESL_1_A	0x420b0

#define _CHICKEN_PIPESL_1_B	0x420b4

drivers/gpu/drm/i915/intel_pm.c

+15 −2
Original line number Diff line number Diff line
@@ -58,6 +58,10 @@ static void bxt_init_clock_gating(struct drm_device *dev) 
{

	struct drm_i915_private *dev_priv = dev->dev_private;



	/* See Bspec note for PSR2_CTL bit 31, Wa#828:bxt */

	I915_WRITE(CHICKEN_PAR1_1,

		   I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);



	/* WaDisableSDEUnitClockGating:bxt */

	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |

		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
@@ -6845,6 +6849,15 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv, 
	I915_WRITE(GEN7_MISCCPCTL, misccpctl);

}



static void skylake_init_clock_gating(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;



	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,kbl */

	I915_WRITE(CHICKEN_PAR1_1,

		   I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);

}



static void broadwell_init_clock_gating(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -7304,9 +7317,9 @@ static void nop_init_clock_gating(struct drm_device *dev) 
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)

{

	if (IS_SKYLAKE(dev_priv))

		dev_priv->display.init_clock_gating = nop_init_clock_gating;

		dev_priv->display.init_clock_gating = skylake_init_clock_gating;

	else if (IS_KABYLAKE(dev_priv))

		dev_priv->display.init_clock_gating = nop_init_clock_gating;

		dev_priv->display.init_clock_gating = skylake_init_clock_gating;

	else if (IS_BROXTON(dev_priv))

		dev_priv->display.init_clock_gating = bxt_init_clock_gating;

	else if (IS_BROADWELL(dev_priv))