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Commit db3c94a7 authored by Kukjin Kim's avatar Kukjin Kim
Browse files

Merge branch 'next-samsung-devel' into next-samsung-devel-2 

Conflicts:
	arch/arm/mach-exynos4/clock.c
	arch/arm/mach-s3c2412/gpio.c
	arch/arm/mach-s5p64x0/dma.c
	arch/arm/mach-s5p64x0/gpiolib.c
parents c9477f38 568f0e27

arch/arm/Kconfig

+0 −3
Original line number Diff line number Diff line
@@ -724,9 +724,6 @@ config ARCH_S3C64XX 
	select SAMSUNG_IRQ_VIC_TIMER

	select SAMSUNG_IRQ_UART

	select S3C_GPIO_TRACK

	select S3C_GPIO_PULL_UPDOWN

	select S3C_GPIO_CFG_S3C24XX

	select S3C_GPIO_CFG_S3C64XX

	select S3C_DEV_NAND

	select USB_ARCH_HAS_OHCI

	select SAMSUNG_GPIOLIB_4BIT

arch/arm/include/asm/hardware/pl080.h

+4 −0
Original line number Diff line number Diff line
@@ -21,6 +21,9 @@ 
 * OneNAND features.

*/



#ifndef ASM_PL080_H

#define ASM_PL080_H



#define PL080_INT_STATUS			(0x00)

#define PL080_TC_STATUS				(0x04)

#define PL080_TC_CLEAR				(0x08)
@@ -138,3 +141,4 @@ struct pl080s_lli { 
	u32	control1;

};



#endif /* ASM_PL080_H */

arch/arm/mach-exynos4/Kconfig

+34 −1
Original line number Diff line number Diff line
@@ -11,7 +11,7 @@ if ARCH_EXYNOS4 


config CPU_EXYNOS4210

	bool

	select S3C_PL330_DMA

	select SAMSUNG_DMADEV

	help

	  Enable EXYNOS4210 CPU support
@@ -131,6 +131,14 @@ config MACH_SMDKV310 
	select S3C_DEV_RTC

	select S3C_DEV_WDT

	select S3C_DEV_I2C1

	select S5P_DEV_FIMC0

	select S5P_DEV_FIMC1

	select S5P_DEV_FIMC2

	select S5P_DEV_FIMC3

	select S5P_DEV_I2C_HDMIPHY

	select S5P_DEV_MFC

	select S5P_DEV_TV

	select S5P_DEV_USB_EHCI

	select S3C_DEV_HSMMC

	select S3C_DEV_HSMMC1

	select S3C_DEV_HSMMC2
@@ -145,6 +153,7 @@ config MACH_SMDKV310 
	select EXYNOS4_SETUP_I2C1

	select EXYNOS4_SETUP_KEYPAD

	select EXYNOS4_SETUP_SDHCI

	select EXYNOS4_SETUP_USB_PHY

	help

	  Machine support for Samsung SMDKV310
@@ -170,19 +179,26 @@ config MACH_UNIVERSAL_C210 
	select S5P_DEV_FIMC1

	select S5P_DEV_FIMC2

	select S5P_DEV_FIMC3

	select S5P_DEV_CSIS0

	select S5P_DEV_FIMD0

	select S3C_DEV_HSMMC

	select S3C_DEV_HSMMC2

	select S3C_DEV_HSMMC3

	select S3C_DEV_I2C1

	select S3C_DEV_I2C3

	select S3C_DEV_I2C5

	select S5P_DEV_I2C_HDMIPHY

	select S5P_DEV_MFC

	select S5P_DEV_ONENAND

	select S5P_DEV_TV

	select EXYNOS4_DEV_PD

	select EXYNOS4_SETUP_FIMD0

	select EXYNOS4_SETUP_I2C1

	select EXYNOS4_SETUP_I2C3

	select EXYNOS4_SETUP_I2C5

	select EXYNOS4_SETUP_SDHCI

	select EXYNOS4_SETUP_FIMC

	select S5P_SETUP_MIPIPHY

	help

	  Machine support for Samsung Mobile Universal S5PC210 Reference

	  Board.
@@ -191,6 +207,8 @@ config MACH_NURI 
	bool "Mobile NURI Board"

	select CPU_EXYNOS4210

	select S3C_DEV_WDT

	select S3C_DEV_RTC

	select S5P_DEV_FIMD0

	select S3C_DEV_HSMMC

	select S3C_DEV_HSMMC2

	select S3C_DEV_HSMMC3
@@ -200,6 +218,7 @@ config MACH_NURI 
	select S5P_DEV_MFC

	select S5P_DEV_USB_EHCI

	select EXYNOS4_DEV_PD

	select EXYNOS4_SETUP_FIMD0

	select EXYNOS4_SETUP_I2C1

	select EXYNOS4_SETUP_I2C3

	select EXYNOS4_SETUP_I2C5
@@ -215,8 +234,22 @@ config MACH_ORIGEN 
	select CPU_EXYNOS4210

	select S3C_DEV_RTC

	select S3C_DEV_WDT

	select S3C_DEV_HSMMC

	select S3C_DEV_HSMMC2

	select S5P_DEV_FIMC0

	select S5P_DEV_FIMC1

	select S5P_DEV_FIMC2

	select S5P_DEV_FIMC3

	select S5P_DEV_FIMD0

	select S5P_DEV_I2C_HDMIPHY

	select S5P_DEV_TV

	select S5P_DEV_USB_EHCI

	select EXYNOS4_DEV_PD

	select SAMSUNG_DEV_BACKLIGHT

	select SAMSUNG_DEV_PWM

	select EXYNOS4_SETUP_FIMD0

	select EXYNOS4_SETUP_SDHCI

	select EXYNOS4_SETUP_USB_PHY

	help

	  Machine support for ORIGEN based on Samsung EXYNOS4210

arch/arm/mach-exynos4/clock.c

+215 −5
Original line number Diff line number Diff line
@@ -111,6 +111,11 @@ struct clk clk_sclk_usbphy1 = { 
	.name		= "sclk_usbphy1",

};



static struct clk dummy_apb_pclk = {

	.name		= "apb_pclk",

	.id		= -1,

};



static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)

{

	return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
@@ -146,6 +151,11 @@ static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable) 
	return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable);

}



static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)

{

	return s5p_gatectrl(S5P_CLKSRC_MASK_TV, clk, enable);

}



static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)

{

	return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
@@ -186,6 +196,16 @@ static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable) 
	return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);

}



static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)

{

	return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);

}



static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)

{

	return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);

}



/* Core list of CMU_CPU side */



static struct clksrc_clk clk_mout_apll = {
@@ -503,13 +523,48 @@ static struct clk init_clocks_off[] = { 
		.enable		= exynos4_clk_ip_fsys_ctrl,

		.ctrlbit	= (1 << 9),

	}, {

		.name		= "pdma",

		.devname	= "s3c-pl330.0",

		.name		= "dac",

		.devname	= "s5p-sdo",

		.enable		= exynos4_clk_ip_tv_ctrl,

		.ctrlbit	= (1 << 2),

	}, {

		.name		= "mixer",

		.devname	= "s5p-mixer",

		.enable		= exynos4_clk_ip_tv_ctrl,

		.ctrlbit	= (1 << 1),

	}, {

		.name		= "vp",

		.devname	= "s5p-mixer",

		.enable		= exynos4_clk_ip_tv_ctrl,

		.ctrlbit	= (1 << 0),

	}, {

		.name		= "hdmi",

		.devname	= "exynos4-hdmi",

		.enable		= exynos4_clk_ip_tv_ctrl,

		.ctrlbit	= (1 << 3),

	}, {

		.name		= "hdmiphy",

		.devname	= "exynos4-hdmi",

		.enable		= exynos4_clk_hdmiphy_ctrl,

		.ctrlbit	= (1 << 0),

	}, {

		.name		= "dacphy",

		.devname	= "s5p-sdo",

		.enable		= exynos4_clk_dac_ctrl,

		.ctrlbit	= (1 << 0),

	}, {

		.name		= "sata",

		.parent		= &clk_aclk_133.clk,

		.enable		= exynos4_clk_ip_fsys_ctrl,

		.ctrlbit	= (1 << 10),

	}, {

		.name		= "dma",

		.devname	= "dma-pl330.0",

		.enable		= exynos4_clk_ip_fsys_ctrl,

		.ctrlbit	= (1 << 0),

	}, {

		.name		= "pdma",

		.devname	= "s3c-pl330.1",

		.name		= "dma",

		.devname	= "dma-pl330.1",

		.enable		= exynos4_clk_ip_fsys_ctrl,

		.ctrlbit	= (1 << 1),

	}, {
@@ -629,6 +684,12 @@ static struct clk init_clocks_off[] = { 
		.parent		= &clk_aclk_100.clk,

		.enable		= exynos4_clk_ip_peril_ctrl,

		.ctrlbit	= (1 << 13),

	}, {

		.name		= "i2c",

		.devname	= "s3c2440-hdmiphy-i2c",

		.parent		= &clk_aclk_100.clk,

		.enable		= exynos4_clk_ip_peril_ctrl,

		.ctrlbit	= (1 << 14),

	}, {

		.name		= "SYSMMU_MDMA",

		.enable		= exynos4_clk_ip_image_ctrl,
@@ -831,6 +892,81 @@ static struct clksrc_sources clkset_mout_mfc = { 
	.nr_sources	= ARRAY_SIZE(clkset_mout_mfc_list),

};



static struct clk *clkset_sclk_dac_list[] = {

	[0] = &clk_sclk_vpll.clk,

	[1] = &clk_sclk_hdmiphy,

};



static struct clksrc_sources clkset_sclk_dac = {

	.sources	= clkset_sclk_dac_list,

	.nr_sources	= ARRAY_SIZE(clkset_sclk_dac_list),

};



static struct clksrc_clk clk_sclk_dac = {

	.clk		= {

		.name		= "sclk_dac",

		.enable		= exynos4_clksrc_mask_tv_ctrl,

		.ctrlbit	= (1 << 8),

	},

	.sources = &clkset_sclk_dac,

	.reg_src = { .reg = S5P_CLKSRC_TV, .shift = 8, .size = 1 },

};



static struct clksrc_clk clk_sclk_pixel = {

	.clk		= {

		.name		= "sclk_pixel",

		.parent = &clk_sclk_vpll.clk,

	},

	.reg_div = { .reg = S5P_CLKDIV_TV, .shift = 0, .size = 4 },

};



static struct clk *clkset_sclk_hdmi_list[] = {

	[0] = &clk_sclk_pixel.clk,

	[1] = &clk_sclk_hdmiphy,

};



static struct clksrc_sources clkset_sclk_hdmi = {

	.sources	= clkset_sclk_hdmi_list,

	.nr_sources	= ARRAY_SIZE(clkset_sclk_hdmi_list),

};



static struct clksrc_clk clk_sclk_hdmi = {

	.clk		= {

		.name		= "sclk_hdmi",

		.enable		= exynos4_clksrc_mask_tv_ctrl,

		.ctrlbit	= (1 << 0),

	},

	.sources = &clkset_sclk_hdmi,

	.reg_src = { .reg = S5P_CLKSRC_TV, .shift = 0, .size = 1 },

};



static struct clk *clkset_sclk_mixer_list[] = {

	[0] = &clk_sclk_dac.clk,

	[1] = &clk_sclk_hdmi.clk,

};



static struct clksrc_sources clkset_sclk_mixer = {

	.sources	= clkset_sclk_mixer_list,

	.nr_sources	= ARRAY_SIZE(clkset_sclk_mixer_list),

};



static struct clksrc_clk clk_sclk_mixer = {

	.clk		= {

		.name		= "sclk_mixer",

		.enable		= exynos4_clksrc_mask_tv_ctrl,

		.ctrlbit	= (1 << 4),

	},

	.sources = &clkset_sclk_mixer,

	.reg_src = { .reg = S5P_CLKSRC_TV, .shift = 4, .size = 1 },

};



static struct clksrc_clk *sclk_tv[] = {

	&clk_sclk_dac,

	&clk_sclk_pixel,

	&clk_sclk_hdmi,

	&clk_sclk_mixer,

};



static struct clksrc_clk clk_dout_mmc0 = {

	.clk		= {

		.name		= "dout_mmc0",
@@ -1157,6 +1293,71 @@ static struct clk_ops exynos4_fout_apll_ops = { 
	.get_rate = exynos4_fout_apll_get_rate,

};



static u32 vpll_div[][8] = {

	{  54000000, 3, 53, 3, 1024, 0, 17, 0 },

	{ 108000000, 3, 53, 2, 1024, 0, 17, 0 },

};



static unsigned long exynos4_vpll_get_rate(struct clk *clk)

{

	return clk->rate;

}



static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)

{

	unsigned int vpll_con0, vpll_con1 = 0;

	unsigned int i;



	/* Return if nothing changed */

	if (clk->rate == rate)

		return 0;



	vpll_con0 = __raw_readl(S5P_VPLL_CON0);

	vpll_con0 &= ~(0x1 << 27 |					\

			PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |	\

			PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |	\

			PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);



	vpll_con1 = __raw_readl(S5P_VPLL_CON1);

	vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT |	\

			PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT |	\

			PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);



	for (i = 0; i < ARRAY_SIZE(vpll_div); i++) {

		if (vpll_div[i][0] == rate) {

			vpll_con0 |= vpll_div[i][1] << PLL46XX_PDIV_SHIFT;

			vpll_con0 |= vpll_div[i][2] << PLL46XX_MDIV_SHIFT;

			vpll_con0 |= vpll_div[i][3] << PLL46XX_SDIV_SHIFT;

			vpll_con1 |= vpll_div[i][4] << PLL46XX_KDIV_SHIFT;

			vpll_con1 |= vpll_div[i][5] << PLL46XX_MFR_SHIFT;

			vpll_con1 |= vpll_div[i][6] << PLL46XX_MRR_SHIFT;

			vpll_con0 |= vpll_div[i][7] << 27;

			break;

		}

	}



	if (i == ARRAY_SIZE(vpll_div)) {

		printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",

				__func__);

		return -EINVAL;

	}



	__raw_writel(vpll_con0, S5P_VPLL_CON0);

	__raw_writel(vpll_con1, S5P_VPLL_CON1);



	/* Wait for VPLL lock */

	while (!(__raw_readl(S5P_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))

		continue;



	clk->rate = rate;

	return 0;

}



static struct clk_ops exynos4_vpll_ops = {

	.get_rate = exynos4_vpll_get_rate,

	.set_rate = exynos4_vpll_set_rate,

};



void __init_or_cpufreq exynos4_setup_clocks(void)

{

	struct clk *xtal_clk;
@@ -1214,6 +1415,7 @@ void __init_or_cpufreq exynos4_setup_clocks(void) 
	clk_fout_apll.ops = &exynos4_fout_apll_ops;

	clk_fout_mpll.rate = mpll;

	clk_fout_epll.rate = epll;

	clk_fout_vpll.ops = &exynos4_vpll_ops;

	clk_fout_vpll.rate = vpll;



	printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
@@ -1241,7 +1443,10 @@ void __init_or_cpufreq exynos4_setup_clocks(void) 
}



static struct clk *clks[] __initdata = {

	/* Nothing here yet */

	&clk_sclk_hdmi27m,

	&clk_sclk_hdmiphy,

	&clk_sclk_usbphy0,

	&clk_sclk_usbphy1,

};



#ifdef CONFIG_PM_SLEEP
@@ -1275,6 +1480,9 @@ void __init exynos4_register_clocks(void) 
	for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)

		s3c_register_clksrc(sysclks[ptr], 1);



	for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)

		s3c_register_clksrc(sclk_tv[ptr], 1);



	s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));

	s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
@@ -1282,5 +1490,7 @@ void __init exynos4_register_clocks(void) 
	s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));



	register_syscore_ops(&exynos4_clock_syscore_ops);

	s3c24xx_register_clock(&dummy_apb_pclk);



	s3c_pwmclk_init();

}

arch/arm/mach-exynos4/cpu.c

+2 −0
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ 
#include <plat/fimc-core.h>

#include <plat/iic-core.h>

#include <plat/reset.h>

#include <plat/tv-core.h>



#include <mach/regs-irq.h>

#include <mach/regs-pmu.h>
@@ -180,6 +181,7 @@ void __init exynos4_map_io(void) 
	s3c_i2c2_setname("s3c2440-i2c");



	s5p_fb_setname(0, "exynos4-fb");

	s5p_hdmi_setname("exynos4-hdmi");

}



void __init exynos4_init_clocks(int xtal)