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Commit db2932ec authored by Bruce Allan's avatar Bruce Allan Committed by David S. Miller
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e1000e: clear PHY wakeup bit after LCD reset on 82577/82578 



Performing a dummy read of the PHY Wakeup Control (WUC) register clears the
wakeup enable bit set by an PHY reset.  If this bit remains set, link
problems may occur.

Signed-off-by: default avatarBruce Allan <bruce.w.allan@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 39305965

drivers/net/e1000e/ich8lan.c

+9 −1
Original line number Diff line number Diff line
@@ -844,7 +844,7 @@ static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) 
	u32 i;

	u32 data, cnf_size, cnf_base_addr, sw_cfg_mask;

	s32 ret_val;

	u16 word_addr, reg_data, reg_addr, phy_page = 0;

	u16 reg, word_addr, reg_data, reg_addr, phy_page = 0;



	ret_val = e1000e_phy_hw_reset_generic(hw);

	if (ret_val)
@@ -859,6 +859,10 @@ static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) 
			return ret_val;

	}



	/* Dummy read to clear the phy wakeup bit after lcd reset */

	if (hw->mac.type == e1000_pchlan)

		e1e_rphy(hw, BM_WUC, &reg);



	/*

	 * Initialize the PHY from the NVM on ICH platforms.  This

	 * is needed due to an issue where the NVM configuration is
@@ -2229,6 +2233,7 @@ static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) 
 **/

static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)

{

	u16 reg;

	u32 ctrl, icr, kab;

	s32 ret_val;
@@ -2304,6 +2309,9 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) 
			hw_dbg(hw, "Auto Read Done did not complete\n");

		}

	}

	/* Dummy read to clear the phy wakeup bit after lcd reset */

	if (hw->mac.type == e1000_pchlan)

		e1e_rphy(hw, BM_WUC, &reg);



	/*

	 * For PCH, this write will make sure that any noise