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Commit daef2262 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'intel'



Jeff Kirsher says:

====================
This series contains updates to ixgbe and e1000e.  The ixgbe patches are
a mix of fixes, cleanup and added functionality.  The first fix is for
traffic classes, where if the mapping has changed reset the NIC.  The other
ixgbe fix resolves an issue where the device lookup neglected to do a
pci_dev_put() to decrement the device reference count.

The ixgbe cleanup was done by Josh, where the auto-negotiation variables
were renamed/cleaned up and refactored.

The remaining patches are from Bruce to do additional cleanup on e1000e as
well as bump the driver version.  Most notably is the cleanup to use the
kernel IEEE MII definitions where possible instead of the local MII
definitions.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 58d7553d c2ade1a4
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+14 −14
Original line number Original line Diff line number Diff line
@@ -624,16 +624,16 @@ static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)


	e_dbg("GG82563 PSCR: %X\n", phy_data);
	e_dbg("GG82563 PSCR: %X\n", phy_data);


	ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
	ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
	if (ret_val)
	if (ret_val)
		return ret_val;
		return ret_val;


	e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
	e1000e_phy_force_speed_duplex_setup(hw, &phy_data);


	/* Reset the phy to commit changes. */
	/* Reset the phy to commit changes. */
	phy_data |= MII_CR_RESET;
	phy_data |= BMCR_RESET;


	ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
	ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
	if (ret_val)
	if (ret_val)
		return ret_val;
		return ret_val;


+9 −8
Original line number Original line Diff line number Diff line
@@ -447,13 +447,13 @@ static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
		break;
		break;
	case e1000_82574:
	case e1000_82574:
	case e1000_82583:
	case e1000_82583:
		ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
		ret_val = e1e_rphy(hw, MII_PHYSID1, &phy_id);
		if (ret_val)
		if (ret_val)
			return ret_val;
			return ret_val;


		phy->id = (u32)(phy_id << 16);
		phy->id = (u32)(phy_id << 16);
		udelay(20);
		udelay(20);
		ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
		ret_val = e1e_rphy(hw, MII_PHYSID2, &phy_id);
		if (ret_val)
		if (ret_val)
			return ret_val;
			return ret_val;


@@ -1328,7 +1328,8 @@ static void e1000_clear_vfta_82571(struct e1000_hw *hw)
			vfta_offset = (hw->mng_cookie.vlan_id >>
			vfta_offset = (hw->mng_cookie.vlan_id >>
				       E1000_VFTA_ENTRY_SHIFT) &
				       E1000_VFTA_ENTRY_SHIFT) &
			    E1000_VFTA_ENTRY_MASK;
			    E1000_VFTA_ENTRY_MASK;
			vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
			vfta_bit_in_reg =
			    1 << (hw->mng_cookie.vlan_id &
				  E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
				  E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
		}
		}
		break;
		break;
+24 −104
Original line number Original line Diff line number Diff line
@@ -29,25 +29,6 @@
#ifndef _E1000_DEFINES_H_
#ifndef _E1000_DEFINES_H_
#define _E1000_DEFINES_H_
#define _E1000_DEFINES_H_


#define E1000_TXD_POPTS_IXSM 0x01       /* Insert IP checksum */
#define E1000_TXD_POPTS_TXSM 0x02       /* Insert TCP/UDP checksum */
#define E1000_TXD_CMD_EOP    0x01000000 /* End of Packet */
#define E1000_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */
#define E1000_TXD_CMD_IC     0x04000000 /* Insert Checksum */
#define E1000_TXD_CMD_RS     0x08000000 /* Report Status */
#define E1000_TXD_CMD_RPS    0x10000000 /* Report Packet Sent */
#define E1000_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */
#define E1000_TXD_CMD_VLE    0x40000000 /* Add VLAN tag */
#define E1000_TXD_CMD_IDE    0x80000000 /* Enable Tidv register */
#define E1000_TXD_STAT_DD    0x00000001 /* Descriptor Done */
#define E1000_TXD_STAT_EC    0x00000002 /* Excess Collisions */
#define E1000_TXD_STAT_LC    0x00000004 /* Late Collisions */
#define E1000_TXD_STAT_TU    0x00000008 /* Transmit underrun */
#define E1000_TXD_CMD_TCP    0x01000000 /* TCP packet */
#define E1000_TXD_CMD_IP     0x02000000 /* IP packet */
#define E1000_TXD_CMD_TSE    0x04000000 /* TCP Seg enable */
#define E1000_TXD_STAT_TC    0x00000004 /* Tx Underrun */

/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
#define REQ_TX_DESCRIPTOR_MULTIPLE  8
#define REQ_TX_DESCRIPTOR_MULTIPLE  8
#define REQ_RX_DESCRIPTOR_MULTIPLE  8
#define REQ_RX_DESCRIPTOR_MULTIPLE  8
@@ -86,7 +67,6 @@
#define E1000_CTRL_EXT_EIAME          0x01000000
#define E1000_CTRL_EXT_EIAME          0x01000000
#define E1000_CTRL_EXT_DRV_LOAD       0x10000000 /* Driver loaded bit for FW */
#define E1000_CTRL_EXT_DRV_LOAD       0x10000000 /* Driver loaded bit for FW */
#define E1000_CTRL_EXT_IAME           0x08000000 /* Interrupt acknowledge Auto-mask */
#define E1000_CTRL_EXT_IAME           0x08000000 /* Interrupt acknowledge Auto-mask */
#define E1000_CTRL_EXT_INT_TIMER_CLR  0x20000000 /* Clear Interrupt timers after IMS clear */
#define E1000_CTRL_EXT_PBA_CLR        0x80000000 /* PBA Clear */
#define E1000_CTRL_EXT_PBA_CLR        0x80000000 /* PBA Clear */
#define E1000_CTRL_EXT_LSECCK         0x00001000
#define E1000_CTRL_EXT_LSECCK         0x00001000
#define E1000_CTRL_EXT_PHYPDEN        0x00100000
#define E1000_CTRL_EXT_PHYPDEN        0x00100000
@@ -273,11 +253,12 @@
#define ADVERTISE_1000_FULL               0x0020
#define ADVERTISE_1000_FULL               0x0020


/* 1000/H is not supported, nor spec-compliant. */
/* 1000/H is not supported, nor spec-compliant. */
#define E1000_ALL_SPEED_DUPLEX ( ADVERTISE_10_HALF |   ADVERTISE_10_FULL | \
#define E1000_ALL_SPEED_DUPLEX	( \
				ADVERTISE_100_HALF |  ADVERTISE_100_FULL | \
	ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \
						     ADVERTISE_1000_FULL)
	ADVERTISE_100_FULL | ADVERTISE_1000_FULL)
#define E1000_ALL_NOT_GIG      ( ADVERTISE_10_HALF |   ADVERTISE_10_FULL | \
#define E1000_ALL_NOT_GIG	( \
				ADVERTISE_100_HALF |  ADVERTISE_100_FULL)
	ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \
	ADVERTISE_100_FULL)
#define E1000_ALL_100_SPEED	(ADVERTISE_100_HALF | ADVERTISE_100_FULL)
#define E1000_ALL_100_SPEED	(ADVERTISE_100_HALF | ADVERTISE_100_FULL)
#define E1000_ALL_10_SPEED	(ADVERTISE_10_HALF | ADVERTISE_10_FULL)
#define E1000_ALL_10_SPEED	(ADVERTISE_10_HALF | ADVERTISE_10_FULL)
#define E1000_ALL_HALF_DUPLEX	(ADVERTISE_10_HALF | ADVERTISE_100_HALF)
#define E1000_ALL_HALF_DUPLEX	(ADVERTISE_10_HALF | ADVERTISE_100_HALF)
@@ -546,7 +527,6 @@
#define E1000_RXCW_SYNCH      0x40000000        /* Receive config synch */
#define E1000_RXCW_SYNCH      0x40000000        /* Receive config synch */


#define E1000_TSYNCTXCTL_VALID		0x00000001 /* Tx timestamp valid */
#define E1000_TSYNCTXCTL_VALID		0x00000001 /* Tx timestamp valid */
#define E1000_TSYNCRXCTL_TYPE_ALL	0x08
#define E1000_TSYNCTXCTL_ENABLED	0x00000010 /* enable Tx timestamping */
#define E1000_TSYNCTXCTL_ENABLED	0x00000010 /* enable Tx timestamping */


#define E1000_TSYNCRXCTL_VALID		0x00000001 /* Rx timestamp valid */
#define E1000_TSYNCRXCTL_VALID		0x00000001 /* Rx timestamp valid */
@@ -583,66 +563,6 @@
			   E1000_GCR_TXDSCW_NO_SNOOP      | \
			   E1000_GCR_TXDSCW_NO_SNOOP      | \
			   E1000_GCR_TXDSCR_NO_SNOOP)
			   E1000_GCR_TXDSCR_NO_SNOOP)


/* PHY Control Register */
#define MII_CR_FULL_DUPLEX      0x0100  /* FDX =1, half duplex =0 */
#define MII_CR_RESTART_AUTO_NEG 0x0200  /* Restart auto negotiation */
#define MII_CR_POWER_DOWN       0x0800  /* Power down */
#define MII_CR_AUTO_NEG_EN      0x1000  /* Auto Neg Enable */
#define MII_CR_LOOPBACK         0x4000  /* 0 = normal, 1 = loopback */
#define MII_CR_RESET            0x8000  /* 0 = normal, 1 = PHY reset */
#define MII_CR_SPEED_1000       0x0040
#define MII_CR_SPEED_100        0x2000
#define MII_CR_SPEED_10         0x0000

/* PHY Status Register */
#define MII_SR_LINK_STATUS       0x0004 /* Link Status 1 = link */
#define MII_SR_AUTONEG_COMPLETE  0x0020 /* Auto Neg Complete */

/* Autoneg Advertisement Register */
#define NWAY_AR_10T_HD_CAPS      0x0020   /* 10T   Half Duplex Capable */
#define NWAY_AR_10T_FD_CAPS      0x0040   /* 10T   Full Duplex Capable */
#define NWAY_AR_100TX_HD_CAPS    0x0080   /* 100TX Half Duplex Capable */
#define NWAY_AR_100TX_FD_CAPS    0x0100   /* 100TX Full Duplex Capable */
#define NWAY_AR_PAUSE            0x0400   /* Pause operation desired */
#define NWAY_AR_ASM_DIR          0x0800   /* Asymmetric Pause Direction bit */

/* Link Partner Ability Register (Base Page) */
#define NWAY_LPAR_100TX_FD_CAPS  0x0100 /* LP 100TX Full Dplx Capable */
#define NWAY_LPAR_PAUSE          0x0400 /* LP Pause operation desired */
#define NWAY_LPAR_ASM_DIR        0x0800 /* LP Asymmetric Pause Direction bit */

/* Autoneg Expansion Register */
#define NWAY_ER_LP_NWAY_CAPS     0x0001 /* LP has Auto Neg Capability */

/* 1000BASE-T Control Register */
#define CR_1000T_HD_CAPS         0x0100 /* Advertise 1000T HD capability */
#define CR_1000T_FD_CAPS         0x0200 /* Advertise 1000T FD capability  */
					/* 0=DTE device */
#define CR_1000T_MS_VALUE        0x0800 /* 1=Configure PHY as Master */
					/* 0=Configure PHY as Slave */
#define CR_1000T_MS_ENABLE       0x1000 /* 1=Master/Slave manual config value */
					/* 0=Automatic Master/Slave config */

/* 1000BASE-T Status Register */
#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
#define SR_1000T_LOCAL_RX_STATUS  0x2000 /* Local receiver OK */


/* PHY 1000 MII Register/Bit Definitions */
/* PHY Registers defined by IEEE */
#define PHY_CONTROL      0x00 /* Control Register */
#define PHY_STATUS       0x01 /* Status Register */
#define PHY_ID1          0x02 /* Phy Id Reg (word 1) */
#define PHY_ID2          0x03 /* Phy Id Reg (word 2) */
#define PHY_AUTONEG_ADV  0x04 /* Autoneg Advertisement */
#define PHY_LP_ABILITY   0x05 /* Link Partner Ability (Base Page) */
#define PHY_AUTONEG_EXP  0x06 /* Autoneg Expansion Reg */
#define PHY_1000T_CTRL   0x09 /* 1000Base-T Control Reg */
#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
#define PHY_EXT_STATUS   0x0F /* Extended Status Reg */

#define PHY_CONTROL_LB   0x4000 /* PHY Loopback bit */

/* NVM Control */
/* NVM Control */
#define E1000_EECD_SK        0x00000001 /* NVM Clock */
#define E1000_EECD_SK        0x00000001 /* NVM Clock */
#define E1000_EECD_CS        0x00000002 /* NVM Chip Select */
#define E1000_EECD_CS        0x00000002 /* NVM Chip Select */
+1 −0
Original line number Original line Diff line number Diff line
@@ -45,6 +45,7 @@
#include <linux/net_tstamp.h>
#include <linux/net_tstamp.h>
#include <linux/ptp_clock_kernel.h>
#include <linux/ptp_clock_kernel.h>
#include <linux/ptp_classify.h>
#include <linux/ptp_classify.h>
#include <linux/mii.h>
#include "hw.h"
#include "hw.h"


struct e1000_info;
struct e1000_info;
+21 −19
Original line number Original line Diff line number Diff line
@@ -418,7 +418,7 @@ static void e1000_set_msglevel(struct net_device *netdev, u32 data)
	adapter->msg_enable = data;
	adapter->msg_enable = data;
}
}


static int e1000_get_regs_len(struct net_device *netdev)
static int e1000_get_regs_len(struct net_device __always_unused *netdev)
{
{
#define E1000_REGS_LEN 32 /* overestimate */
#define E1000_REGS_LEN 32 /* overestimate */
	return E1000_REGS_LEN * sizeof(u32);
	return E1000_REGS_LEN * sizeof(u32);
@@ -473,7 +473,7 @@ static void e1000_get_regs(struct net_device *netdev,
		regs_buff[23] = regs_buff[13]; /* mdix mode */
		regs_buff[23] = regs_buff[13]; /* mdix mode */
	}
	}
	regs_buff[21] = 0;	/* was idle_errors */
	regs_buff[21] = 0;	/* was idle_errors */
	e1e_rphy(hw, PHY_1000T_STATUS, &phy_data);
	e1e_rphy(hw, MII_STAT1000, &phy_data);
	regs_buff[24] = (u32)phy_data;	/* phy local receiver status */
	regs_buff[24] = (u32)phy_data;	/* phy local receiver status */
	regs_buff[25] = regs_buff[24];	/* phy remote receiver status */
	regs_buff[25] = regs_buff[24];	/* phy remote receiver status */
}
}
@@ -934,7 +934,7 @@ static int e1000_eeprom_test(struct e1000_adapter *adapter, u64 *data)
	return *data;
	return *data;
}
}


static irqreturn_t e1000_test_intr(int irq, void *data)
static irqreturn_t e1000_test_intr(int __always_unused irq, void *data)
{
{
	struct net_device *netdev = (struct net_device *) data;
	struct net_device *netdev = (struct net_device *) data;
	struct e1000_adapter *adapter = netdev_priv(netdev);
	struct e1000_adapter *adapter = netdev_priv(netdev);
@@ -1284,7 +1284,7 @@ static int e1000_integrated_phy_loopback(struct e1000_adapter *adapter)


	if (hw->phy.type == e1000_phy_ife) {
	if (hw->phy.type == e1000_phy_ife) {
		/* force 100, set loopback */
		/* force 100, set loopback */
		e1e_wphy(hw, PHY_CONTROL, 0x6100);
		e1e_wphy(hw, MII_BMCR, 0x6100);


		/* Now set up the MAC to the same speed/duplex as the PHY. */
		/* Now set up the MAC to the same speed/duplex as the PHY. */
		ctrl_reg = er32(CTRL);
		ctrl_reg = er32(CTRL);
@@ -1307,9 +1307,9 @@ static int e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
		/* Auto-MDI/MDIX Off */
		/* Auto-MDI/MDIX Off */
		e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
		e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
		/* reset to update Auto-MDI/MDIX */
		/* reset to update Auto-MDI/MDIX */
		e1e_wphy(hw, PHY_CONTROL, 0x9140);
		e1e_wphy(hw, MII_BMCR, 0x9140);
		/* autoneg off */
		/* autoneg off */
		e1e_wphy(hw, PHY_CONTROL, 0x8140);
		e1e_wphy(hw, MII_BMCR, 0x8140);
		break;
		break;
	case e1000_phy_gg82563:
	case e1000_phy_gg82563:
		e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, 0x1CC);
		e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, 0x1CC);
@@ -1363,7 +1363,7 @@ static int e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
	}
	}


	/* force 1000, set loopback */
	/* force 1000, set loopback */
	e1e_wphy(hw, PHY_CONTROL, 0x4140);
	e1e_wphy(hw, MII_BMCR, 0x4140);
	mdelay(250);
	mdelay(250);


	/* Now set up the MAC to the same speed/duplex as the PHY. */
	/* Now set up the MAC to the same speed/duplex as the PHY. */
@@ -1538,10 +1538,10 @@ static void e1000_loopback_cleanup(struct e1000_adapter *adapter)
		hw->mac.autoneg = 1;
		hw->mac.autoneg = 1;
		if (hw->phy.type == e1000_phy_gg82563)
		if (hw->phy.type == e1000_phy_gg82563)
			e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, 0x180);
			e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, 0x180);
		e1e_rphy(hw, PHY_CONTROL, &phy_reg);
		e1e_rphy(hw, MII_BMCR, &phy_reg);
		if (phy_reg & MII_CR_LOOPBACK) {
		if (phy_reg & BMCR_LOOPBACK) {
			phy_reg &= ~MII_CR_LOOPBACK;
			phy_reg &= ~BMCR_LOOPBACK;
			e1e_wphy(hw, PHY_CONTROL, phy_reg);
			e1e_wphy(hw, MII_BMCR, phy_reg);
			if (hw->phy.ops.commit)
			if (hw->phy.ops.commit)
				hw->phy.ops.commit(hw);
				hw->phy.ops.commit(hw);
		}
		}
@@ -1705,7 +1705,8 @@ static int e1000_link_test(struct e1000_adapter *adapter, u64 *data)
	return *data;
	return *data;
}
}


static int e1000e_get_sset_count(struct net_device *netdev, int sset)
static int e1000e_get_sset_count(struct net_device __always_unused *netdev,
				 int sset)
{
{
	switch (sset) {
	switch (sset) {
	case ETH_SS_TEST:
	case ETH_SS_TEST:
@@ -1968,7 +1969,7 @@ static int e1000_nway_reset(struct net_device *netdev)
}
}


static void e1000_get_ethtool_stats(struct net_device *netdev,
static void e1000_get_ethtool_stats(struct net_device *netdev,
				    struct ethtool_stats *stats,
				    struct ethtool_stats __always_unused *stats,
				    u64 *data)
				    u64 *data)
{
{
	struct e1000_adapter *adapter = netdev_priv(netdev);
	struct e1000_adapter *adapter = netdev_priv(netdev);
@@ -1997,8 +1998,8 @@ static void e1000_get_ethtool_stats(struct net_device *netdev,
	}
	}
}
}


static void e1000_get_strings(struct net_device *netdev, u32 stringset,
static void e1000_get_strings(struct net_device __always_unused *netdev,
			      u8 *data)
			      u32 stringset, u8 *data)
{
{
	u8 *p = data;
	u8 *p = data;
	int i;
	int i;
@@ -2018,7 +2019,8 @@ static void e1000_get_strings(struct net_device *netdev, u32 stringset,
}
}


static int e1000_get_rxnfc(struct net_device *netdev,
static int e1000_get_rxnfc(struct net_device *netdev,
			   struct ethtool_rxnfc *info, u32 *rule_locs)
			   struct ethtool_rxnfc *info,
			   u32 __always_unused *rule_locs)
{
{
	info->data = 0;
	info->data = 0;


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