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Commit dab7f7fe authored by Rene Sapiens's avatar Rene Sapiens Committed by Omar Ramirez Luna
Browse files

staging: tidspbridge: set6 remove hungarian from structs 



hungarian notation will be removed from the elements inside
structures, the next varibles will be renamed:

Original:		Replacement:
pfn_write               write
pf_phase_split          phase_split
ul_alignment            alignment
ul_bufsize              bufsize
ul_bufsize_rms          bufsize_rms
ul_chnl_buf_size        chnl_buf_size
ul_chnl_offset          chnl_offset
ul_code_mem_seg_mask    code_mem_seg_mask
ul_dais_arg             dais_arg
ul_data1                data1
ul_data_mem_seg_mask    data_mem_seg_mask
ul_dsp_addr             dsp_addr
ul_dsp_res_addr         dsp_res_addr
ul_dsp_size             dsp_size
ul_dsp_va               dsp_va
ul_dsp_virt             dsp_virt
ul_entry                entry
ul_external_mem_size    external_mem_size
ul_fxn_addrs            fxn_addrs
ul_gpp_pa               gpp_pa

Signed-off-by: default avatarRene Sapiens <rene.sapiens@ti.com>
Signed-off-by: default avatarArmando Uribe <x0095078@ti.com>
Signed-off-by: default avatarOmar Ramirez Luna <omar.ramirez@ti.com>
parent 09f13304

drivers/staging/tidspbridge/core/io_sm.c

+25 −25
Original line number Diff line number Diff line
@@ -121,7 +121,7 @@ struct io_mgr { 
	u32 ul_gpp_read_pointer;	/* GPP Read pointer to Trace buffer */

	u8 *pmsg;

	u32 ul_gpp_va;

	u32 ul_dsp_va;

	u32 dsp_va;

#endif

	/* IO Dpc */

	u32 dpc_req;		/* Number of requested DPC's. */
@@ -421,7 +421,7 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr) 
		ul_gpp_va = host_res->mem_base[1];

		/* This is the virtual uncached ioremapped address!!! */

		/* Why can't we directly take the DSPVA from the symbols? */

		ul_dsp_va = hio_mgr->ext_proc_info.ty_tlb[0].ul_dsp_virt;

		ul_dsp_va = hio_mgr->ext_proc_info.ty_tlb[0].dsp_virt;

		ul_seg_size = (shm0_end - ul_dsp_va) * hio_mgr->word_size;

		ul_seg1_size =

		    (ul_ext_end - ul_dyn_ext_base) * hio_mgr->word_size;
@@ -527,13 +527,13 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr) 
				 * This is the physical address written to

				 * DSP MMU.

				 */

				ae_proc[ndx].ul_gpp_pa = pa_curr;

				ae_proc[ndx].gpp_pa = pa_curr;

				/*

				 * This is the virtual uncached ioremapped

				 * address!!!

				 */

				ae_proc[ndx].ul_gpp_va = gpp_va_curr;

				ae_proc[ndx].ul_dsp_va =

				ae_proc[ndx].dsp_va =

				    va_curr / hio_mgr->word_size;

				ae_proc[ndx].ul_size = page_size[i];

				ae_proc[ndx].endianism = HW_LITTLE_ENDIAN;
@@ -541,9 +541,9 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr) 
				ae_proc[ndx].mixed_mode = HW_MMU_CPUES;

				dev_dbg(bridge, "shm MMU TLB entry PA %x"

					" VA %x DSP_VA %x Size %x\n",

					ae_proc[ndx].ul_gpp_pa,

					ae_proc[ndx].gpp_pa,

					ae_proc[ndx].ul_gpp_va,

					ae_proc[ndx].ul_dsp_va *

					ae_proc[ndx].dsp_va *

					hio_mgr->word_size, page_size[i]);

				ndx++;

			} else {
@@ -556,9 +556,9 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr) 
				dev_dbg(bridge,

					"shm MMU PTE entry PA %x"

					" VA %x DSP_VA %x Size %x\n",

					ae_proc[ndx].ul_gpp_pa,

					ae_proc[ndx].gpp_pa,

					ae_proc[ndx].ul_gpp_va,

					ae_proc[ndx].ul_dsp_va *

					ae_proc[ndx].dsp_va *

					hio_mgr->word_size, page_size[i]);

				if (status)

					goto func_end;
@@ -587,32 +587,32 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr) 
		     ul_gpp_pa - 0x100000

		     && hio_mgr->ext_proc_info.ty_tlb[i].ul_gpp_phys <=

		     ul_gpp_pa + ul_seg_size)

		    || (hio_mgr->ext_proc_info.ty_tlb[i].ul_dsp_virt >

		    || (hio_mgr->ext_proc_info.ty_tlb[i].dsp_virt >

			ul_dsp_va - 0x100000 / hio_mgr->word_size

			&& hio_mgr->ext_proc_info.ty_tlb[i].ul_dsp_virt <=

			&& hio_mgr->ext_proc_info.ty_tlb[i].dsp_virt <=

			ul_dsp_va + ul_seg_size / hio_mgr->word_size)) {

			dev_dbg(bridge,

				"CDB MMU entry %d conflicts with "

				"shm.\n\tCDB: GppPa %x, DspVa %x.\n\tSHM: "

				"GppPa %x, DspVa %x, Bytes %x.\n", i,

				hio_mgr->ext_proc_info.ty_tlb[i].ul_gpp_phys,

				hio_mgr->ext_proc_info.ty_tlb[i].ul_dsp_virt,

				hio_mgr->ext_proc_info.ty_tlb[i].dsp_virt,

				ul_gpp_pa, ul_dsp_va, ul_seg_size);

			status = -EPERM;

		} else {

			if (ndx < MAX_LOCK_TLB_ENTRIES) {

				ae_proc[ndx].ul_dsp_va =

				ae_proc[ndx].dsp_va =

				    hio_mgr->ext_proc_info.ty_tlb[i].

				    ul_dsp_virt;

				ae_proc[ndx].ul_gpp_pa =

				    dsp_virt;

				ae_proc[ndx].gpp_pa =

				    hio_mgr->ext_proc_info.ty_tlb[i].

				    ul_gpp_phys;

				ae_proc[ndx].ul_gpp_va = 0;

				/* 1 MB */

				ae_proc[ndx].ul_size = 0x100000;

				dev_dbg(bridge, "shm MMU entry PA %x "

					"DSP_VA 0x%x\n", ae_proc[ndx].ul_gpp_pa,

					ae_proc[ndx].ul_dsp_va);

					"DSP_VA 0x%x\n", ae_proc[ndx].gpp_pa,

					ae_proc[ndx].dsp_va);

				ndx++;

			} else {

				status = hio_mgr->intf_fxns->brd_mem_map
@@ -620,7 +620,7 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr) 
				     hio_mgr->ext_proc_info.ty_tlb[i].

				     ul_gpp_phys,

				     hio_mgr->ext_proc_info.ty_tlb[i].

				     ul_dsp_virt, 0x100000, map_attrs,

				     dsp_virt, 0x100000, map_attrs,

				     NULL);

			}

		}
@@ -647,8 +647,8 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr) 
	}



	for (i = ndx; i < BRDIOCTL_NUMOFMMUTLB; i++) {

		ae_proc[i].ul_dsp_va = 0;

		ae_proc[i].ul_gpp_pa = 0;

		ae_proc[i].dsp_va = 0;

		ae_proc[i].gpp_pa = 0;

		ae_proc[i].ul_gpp_va = 0;

		ae_proc[i].ul_size = 0;

	}
@@ -668,12 +668,12 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr) 
		status = -EFAULT;

		goto func_end;

	} else {

		if (ae_proc[0].ul_dsp_va > ul_shm_base) {

		if (ae_proc[0].dsp_va > ul_shm_base) {

			status = -EPERM;

			goto func_end;

		}

		/* ul_shm_base may not be at ul_dsp_va address */

		ul_shm_base_offset = (ul_shm_base - ae_proc[0].ul_dsp_va) *

		ul_shm_base_offset = (ul_shm_base - ae_proc[0].dsp_va) *

		    hio_mgr->word_size;

		/*

		 * bridge_dev_ctrl() will set dev context dsp-mmu info. In
@@ -698,7 +698,7 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr) 
		}

		/* Register SM */

		status =

		    register_shm_segs(hio_mgr, cod_man, ae_proc[0].ul_gpp_pa);

		    register_shm_segs(hio_mgr, cod_man, ae_proc[0].gpp_pa);

	}



	hio_mgr->shared_mem = (struct shm *)ul_shm_base;
@@ -771,7 +771,7 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr) 
	if (!hio_mgr->pmsg)

		status = -ENOMEM;



	hio_mgr->ul_dsp_va = ul_dsp_va;

	hio_mgr->dsp_va = ul_dsp_va;

	hio_mgr->ul_gpp_va = (ul_gpp_va + ul_seg1_size + ul_pad_size);



#endif
@@ -1544,7 +1544,7 @@ static int register_shm_segs(struct io_mgr *hio_mgr, 
		ul_gpp_phys = hio_mgr->ext_proc_info.ty_tlb[0].ul_gpp_phys;

		/* Get size in bytes */

		ul_dsp_virt =

		    hio_mgr->ext_proc_info.ty_tlb[0].ul_dsp_virt *

		    hio_mgr->ext_proc_info.ty_tlb[0].dsp_virt *

		    hio_mgr->word_size;

		/*

		 * Calc byte offset used to convert GPP phys <-> DSP byte
@@ -1694,7 +1694,7 @@ void print_dsp_debug_trace(struct io_mgr *hio_mgr) 
		    *(u32 *) (hio_mgr->ul_trace_buffer_current);

		ul_gpp_cur_pointer =

		    hio_mgr->ul_gpp_va + (ul_gpp_cur_pointer -

					  hio_mgr->ul_dsp_va);

					  hio_mgr->dsp_va);



		/* No new debug messages available yet */

		if (ul_gpp_cur_pointer == hio_mgr->ul_gpp_read_pointer) {

drivers/staging/tidspbridge/core/tiomap3430.c

+8 −8
Original line number Diff line number Diff line
@@ -401,7 +401,7 @@ static int bridge_brd_start(struct bridge_dev_context *dev_ctxt, 
	ul_shm_base_virt *= DSPWORDSIZE;

	DBC_ASSERT(ul_shm_base_virt != 0);

	/* DSP Virtual address */

	ul_tlb_base_virt = dev_context->atlb_entry[0].ul_dsp_va;

	ul_tlb_base_virt = dev_context->atlb_entry[0].dsp_va;

	DBC_ASSERT(ul_tlb_base_virt <= ul_shm_base_virt);

	ul_shm_offset_virt =

	    ul_shm_base_virt - (ul_tlb_base_virt * DSPWORDSIZE);
@@ -466,19 +466,19 @@ static int bridge_brd_start(struct bridge_dev_context *dev_ctxt, 
				.mixed_size = e->mixed_mode,

			};



			if (!e->ul_gpp_pa || !e->ul_dsp_va)

			if (!e->gpp_pa || !e->dsp_va)

				continue;



			dev_dbg(bridge,

					"MMU %d, pa: 0x%x, va: 0x%x, size: 0x%x",

					itmp_entry_ndx,

					e->ul_gpp_pa,

					e->ul_dsp_va,

					e->gpp_pa,

					e->dsp_va,

					e->ul_size);



			hw_mmu_tlb_add(dev_context->dsp_mmu_base,

					e->ul_gpp_pa,

					e->ul_dsp_va,

					e->gpp_pa,

					e->dsp_va,

					e->ul_size,

					itmp_entry_ndx,

					&map_attrs, 1, 1);
@@ -771,8 +771,8 @@ static int bridge_dev_create(struct bridge_dev_context 
	/*  Clear dev context MMU table entries.

	 *  These get set on bridge_io_on_loaded() call after program loaded. */

	for (entry_ndx = 0; entry_ndx < BRDIOCTL_NUMOFMMUTLB; entry_ndx++) {

		dev_context->atlb_entry[entry_ndx].ul_gpp_pa =

		    dev_context->atlb_entry[entry_ndx].ul_dsp_va = 0;

		dev_context->atlb_entry[entry_ndx].gpp_pa =

		    dev_context->atlb_entry[entry_ndx].dsp_va = 0;

	}

	dev_context->dsp_base_addr = (u32) MEM_LINEAR_ADDRESS((void *)

								 (config_param->

drivers/staging/tidspbridge/core/tiomap_io.c

+2 −2
Original line number Diff line number Diff line
@@ -134,7 +134,7 @@ int read_ext_dsp_data(struct bridge_dev_context *dev_ctxt, 


		if (!status) {

			ul_tlb_base_virt =

			    dev_context->atlb_entry[0].ul_dsp_va * DSPWORDSIZE;

			    dev_context->atlb_entry[0].dsp_va * DSPWORDSIZE;

			DBC_ASSERT(ul_tlb_base_virt <= ul_shm_base_virt);

			dw_ext_prog_virt_mem =

			    dev_context->atlb_entry[0].ul_gpp_va;
@@ -319,7 +319,7 @@ int write_ext_dsp_data(struct bridge_dev_context *dev_context, 


		if (!ret) {

			ul_tlb_base_virt =

			    dev_context->atlb_entry[0].ul_dsp_va * DSPWORDSIZE;

			    dev_context->atlb_entry[0].dsp_va * DSPWORDSIZE;

			DBC_ASSERT(ul_tlb_base_virt <= ul_shm_base_virt);



			if (symbols_reloaded) {

drivers/staging/tidspbridge/gen/uuidutil.c

+2 −2
Original line number Diff line number Diff line
@@ -45,7 +45,7 @@ void uuid_uuid_to_string(struct dsp_uuid *uuid_obj, char *sz_uuid, 


	i = snprintf(sz_uuid, size,

		     "%.8X_%.4X_%.4X_%.2X%.2X_%.2X%.2X%.2X%.2X%.2X%.2X",

		     uuid_obj->ul_data1, uuid_obj->us_data2, uuid_obj->us_data3,

		     uuid_obj->data1, uuid_obj->us_data2, uuid_obj->us_data3,

		     uuid_obj->uc_data4, uuid_obj->uc_data5,

		     uuid_obj->uc_data6[0], uuid_obj->uc_data6[1],

		     uuid_obj->uc_data6[2], uuid_obj->uc_data6[3],
@@ -79,7 +79,7 @@ void uuid_uuid_from_string(char *sz_uuid, struct dsp_uuid *uuid_obj) 
{

	s32 j;



	uuid_obj->ul_data1 = uuid_hex_to_bin(sz_uuid, 8);

	uuid_obj->data1 = uuid_hex_to_bin(sz_uuid, 8);

	sz_uuid += 8;



	/* Step over underscore */

drivers/staging/tidspbridge/include/dspbridge/cmmdefs.h

+2 −2
Original line number Diff line number Diff line
@@ -29,7 +29,7 @@ struct cmm_mgrattrs { 
/* Attributes for CMM_AllocBuf() & CMM_AllocDesc() */

struct cmm_attrs {

	u32 ul_seg_id;		/*  1,2... are SM segments. 0 is not. */

	u32 ul_alignment;	/*  0,1,2,4....ul_min_block_size */

	u32 alignment;		/*  0,1,2,4....ul_min_block_size */

};



/*
@@ -57,7 +57,7 @@ struct cmm_seginfo { 
	u32 gpp_base_pa;	/* Start Phys addr of Gpp SM seg */

	u32 ul_gpp_size;	/* Size of Gpp SM seg in bytes */

	u32 dsp_base_va;	/* DSP virt base byte address */

	u32 ul_dsp_size;	/* DSP seg size in bytes */

	u32 dsp_size;		/* DSP seg size in bytes */

	/* # of current GPP allocations from this segment */

	u32 ul_in_use_cnt;

	u32 seg_base_va;	/* Start Virt address of SM seg */