Loading drivers/gpu/msm/adreno-gpulist.h +1 −1 Original line number Diff line number Diff line Loading @@ -347,7 +347,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { .minor = 0, .patchid = ANY_ID, .features = ADRENO_64BIT | ADRENO_RPMH | ADRENO_IFPC | ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_LM | ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_IOCOHERENT, .sqefw_name = "a630_sqe.fw", .zap_name = "a630_zap", Loading drivers/gpu/msm/adreno_a6xx.c +17 −0 Original line number Diff line number Diff line Loading @@ -770,10 +770,27 @@ static void a6xx_start(struct adreno_device *adreno_dev) */ if (ADRENO_FEATURE(adreno_dev, ADRENO_LM) && test_bit(ADRENO_LM_CTRL, &adreno_dev->pwrctrl_flag)) { int result; struct gmu_device *gmu = &device->gmu; struct device *dev = &gmu->pdev->dev; kgsl_gmu_regwrite(device, A6XX_GPU_GMU_CX_GMU_PWR_THRESHOLD, GPU_LIMIT_THRESHOLD_ENABLE | lm_limit(adreno_dev)); kgsl_gmu_regwrite(device, A6XX_GMU_AO_SPARE_CNTL, 1); kgsl_gmu_regwrite(device, A6XX_GPU_GMU_CX_GMU_ISENSE_CTRL, 0x1); gmu->lm_config.lm_type = 1; gmu->lm_config.lm_sensor_type = 1; gmu->lm_config.throttle_config = 1; gmu->lm_config.idle_throttle_en = 0; gmu->lm_config.acd_en = 0; gmu->bcl_config = 0; gmu->lm_dcvs_level = 0; result = hfi_send_lmconfig(gmu); if (result) dev_err(dev, "Failure enabling limits management (%d)\n", result); } } Loading drivers/gpu/msm/kgsl_hfi.c +0 −18 Original line number Diff line number Diff line Loading @@ -611,24 +611,6 @@ int hfi_start(struct gmu_device *gmu, uint32_t boot_state) if (result) return result; if (ADRENO_FEATURE(adreno_dev, ADRENO_LM) && test_bit(ADRENO_LM_CTRL, &adreno_dev->pwrctrl_flag)) { gmu->lm_config.lm_type = 1; gmu->lm_config.lm_sensor_type = 1; gmu->lm_config.throttle_config = 1; gmu->lm_config.idle_throttle_en = 0; gmu->lm_config.acd_en = 0; gmu->bcl_config = 0; gmu->lm_dcvs_level = 0; result = hfi_send_lmconfig(gmu); if (result) { dev_err(dev, "Failure enabling LM (%d)\n", result); return result; } } /* Tell the GMU we are sending no more HFIs until the next boot */ if (ADRENO_QUIRK(adreno_dev, ADRENO_QUIRK_HFI_USE_REG)) { result = hfi_send_test(gmu); Loading drivers/gpu/msm/kgsl_hfi.h +1 −0 Original line number Diff line number Diff line Loading @@ -360,4 +360,5 @@ int hfi_send_dcvs_vote(struct gmu_device *gmu, uint32_t perf_idx, uint32_t bw_idx, enum rpm_ack_type ack_type); int hfi_notify_slumber(struct gmu_device *gmu, uint32_t init_perf_idx, uint32_t init_bw_idx); int hfi_send_lmconfig(struct gmu_device *gmu); #endif /* __KGSL_HFI_H */ Loading
drivers/gpu/msm/adreno-gpulist.h +1 −1 Original line number Diff line number Diff line Loading @@ -347,7 +347,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { .minor = 0, .patchid = ANY_ID, .features = ADRENO_64BIT | ADRENO_RPMH | ADRENO_IFPC | ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_LM | ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_IOCOHERENT, .sqefw_name = "a630_sqe.fw", .zap_name = "a630_zap", Loading
drivers/gpu/msm/adreno_a6xx.c +17 −0 Original line number Diff line number Diff line Loading @@ -770,10 +770,27 @@ static void a6xx_start(struct adreno_device *adreno_dev) */ if (ADRENO_FEATURE(adreno_dev, ADRENO_LM) && test_bit(ADRENO_LM_CTRL, &adreno_dev->pwrctrl_flag)) { int result; struct gmu_device *gmu = &device->gmu; struct device *dev = &gmu->pdev->dev; kgsl_gmu_regwrite(device, A6XX_GPU_GMU_CX_GMU_PWR_THRESHOLD, GPU_LIMIT_THRESHOLD_ENABLE | lm_limit(adreno_dev)); kgsl_gmu_regwrite(device, A6XX_GMU_AO_SPARE_CNTL, 1); kgsl_gmu_regwrite(device, A6XX_GPU_GMU_CX_GMU_ISENSE_CTRL, 0x1); gmu->lm_config.lm_type = 1; gmu->lm_config.lm_sensor_type = 1; gmu->lm_config.throttle_config = 1; gmu->lm_config.idle_throttle_en = 0; gmu->lm_config.acd_en = 0; gmu->bcl_config = 0; gmu->lm_dcvs_level = 0; result = hfi_send_lmconfig(gmu); if (result) dev_err(dev, "Failure enabling limits management (%d)\n", result); } } Loading
drivers/gpu/msm/kgsl_hfi.c +0 −18 Original line number Diff line number Diff line Loading @@ -611,24 +611,6 @@ int hfi_start(struct gmu_device *gmu, uint32_t boot_state) if (result) return result; if (ADRENO_FEATURE(adreno_dev, ADRENO_LM) && test_bit(ADRENO_LM_CTRL, &adreno_dev->pwrctrl_flag)) { gmu->lm_config.lm_type = 1; gmu->lm_config.lm_sensor_type = 1; gmu->lm_config.throttle_config = 1; gmu->lm_config.idle_throttle_en = 0; gmu->lm_config.acd_en = 0; gmu->bcl_config = 0; gmu->lm_dcvs_level = 0; result = hfi_send_lmconfig(gmu); if (result) { dev_err(dev, "Failure enabling LM (%d)\n", result); return result; } } /* Tell the GMU we are sending no more HFIs until the next boot */ if (ADRENO_QUIRK(adreno_dev, ADRENO_QUIRK_HFI_USE_REG)) { result = hfi_send_test(gmu); Loading
drivers/gpu/msm/kgsl_hfi.h +1 −0 Original line number Diff line number Diff line Loading @@ -360,4 +360,5 @@ int hfi_send_dcvs_vote(struct gmu_device *gmu, uint32_t perf_idx, uint32_t bw_idx, enum rpm_ack_type ack_type); int hfi_notify_slumber(struct gmu_device *gmu, uint32_t init_perf_idx, uint32_t init_bw_idx); int hfi_send_lmconfig(struct gmu_device *gmu); #endif /* __KGSL_HFI_H */