Loading drivers/soc/qcom/llcc-core.c +0 −6 Original line number Diff line number Diff line Loading @@ -20,7 +20,6 @@ #include <linux/regmap.h> /* Config registers offsets*/ #define COMMON_CFG0 0x00030004 #define DRP_ECC_ERROR_CFG 0x00040000 /* TRP, DRP interrupt register offsets */ Loading @@ -29,7 +28,6 @@ #define TRP_INTERRUPT_0_ENABLE 0x00020488 #define DRP_INTERRUPT_ENABLE 0x0004100C #define DATA_RAM_ECC_ENABLE 0x1 #define SB_ERROR_THRESHOLD 0x1 #define SB_ERROR_THRESHOLD_SHIFT 24 #define SB_DB_TRP_INTERRUPT_ENABLE 0x3 Loading @@ -50,10 +48,6 @@ static void qcom_llcc_core_setup(struct regmap *llcc_regmap) regmap_update_bits(llcc_regmap, TRP_INTERRUPT_0_ENABLE, SB_DB_TRP_INTERRUPT_ENABLE, SB_DB_TRP_INTERRUPT_ENABLE); /* Enable ECC for for data ram */ regmap_update_bits(llcc_regmap, COMMON_CFG0, DATA_RAM_ECC_ENABLE, DATA_RAM_ECC_ENABLE); /* Enable SB error for Data RAM */ sb_err_threshold = (SB_ERROR_THRESHOLD << SB_ERROR_THRESHOLD_SHIFT); regmap_write(llcc_regmap, DRP_ECC_ERROR_CFG, sb_err_threshold); Loading drivers/soc/qcom/llcc-slice.c +0 −12 Original line number Diff line number Diff line Loading @@ -49,8 +49,6 @@ #define LLCC_TRP_STATUSn(n) (4 + n * 0x1000) #define LLCC_TRP_ATTR0_CFGn(n) (0x21000 + 0x8 * n) #define LLCC_TRP_ATTR1_CFGn(n) (0x21004 + 0x8 * n) #define LLCC_TRP_PCB_ACT 0x23204 #define LLCC_TRP_SCID_DIS_CAP_ALLOC 0x23200 /** * Driver data for llcc Loading Loading @@ -320,8 +318,6 @@ static void qcom_llcc_cfg_program(struct platform_device *pdev) u32 attr0_cfg; u32 attr1_val; u32 attr0_val; u32 pcb = 0; u32 cad = 0; u32 max_cap_cacheline; u32 sz; const struct llcc_slice_config *llcc_table; Loading Loading @@ -358,14 +354,6 @@ static void qcom_llcc_cfg_program(struct platform_device *pdev) regmap_write(drv->llcc_map, attr1_cfg, attr1_val); regmap_write(drv->llcc_map, attr0_cfg, attr0_val); /* Write the retain on power collapse bit for each scid */ pcb |= llcc_table[i].retain_on_pc << llcc_table[i].slice_id; regmap_write(drv->llcc_map, LLCC_TRP_PCB_ACT, pcb); /* Disable capacity alloc */ cad |= llcc_table[i].dis_cap_alloc << llcc_table[i].slice_id; regmap_write(drv->llcc_map, LLCC_TRP_SCID_DIS_CAP_ALLOC, cad); /* Make sure that the SCT is programmed before activating */ mb(); Loading Loading
drivers/soc/qcom/llcc-core.c +0 −6 Original line number Diff line number Diff line Loading @@ -20,7 +20,6 @@ #include <linux/regmap.h> /* Config registers offsets*/ #define COMMON_CFG0 0x00030004 #define DRP_ECC_ERROR_CFG 0x00040000 /* TRP, DRP interrupt register offsets */ Loading @@ -29,7 +28,6 @@ #define TRP_INTERRUPT_0_ENABLE 0x00020488 #define DRP_INTERRUPT_ENABLE 0x0004100C #define DATA_RAM_ECC_ENABLE 0x1 #define SB_ERROR_THRESHOLD 0x1 #define SB_ERROR_THRESHOLD_SHIFT 24 #define SB_DB_TRP_INTERRUPT_ENABLE 0x3 Loading @@ -50,10 +48,6 @@ static void qcom_llcc_core_setup(struct regmap *llcc_regmap) regmap_update_bits(llcc_regmap, TRP_INTERRUPT_0_ENABLE, SB_DB_TRP_INTERRUPT_ENABLE, SB_DB_TRP_INTERRUPT_ENABLE); /* Enable ECC for for data ram */ regmap_update_bits(llcc_regmap, COMMON_CFG0, DATA_RAM_ECC_ENABLE, DATA_RAM_ECC_ENABLE); /* Enable SB error for Data RAM */ sb_err_threshold = (SB_ERROR_THRESHOLD << SB_ERROR_THRESHOLD_SHIFT); regmap_write(llcc_regmap, DRP_ECC_ERROR_CFG, sb_err_threshold); Loading
drivers/soc/qcom/llcc-slice.c +0 −12 Original line number Diff line number Diff line Loading @@ -49,8 +49,6 @@ #define LLCC_TRP_STATUSn(n) (4 + n * 0x1000) #define LLCC_TRP_ATTR0_CFGn(n) (0x21000 + 0x8 * n) #define LLCC_TRP_ATTR1_CFGn(n) (0x21004 + 0x8 * n) #define LLCC_TRP_PCB_ACT 0x23204 #define LLCC_TRP_SCID_DIS_CAP_ALLOC 0x23200 /** * Driver data for llcc Loading Loading @@ -320,8 +318,6 @@ static void qcom_llcc_cfg_program(struct platform_device *pdev) u32 attr0_cfg; u32 attr1_val; u32 attr0_val; u32 pcb = 0; u32 cad = 0; u32 max_cap_cacheline; u32 sz; const struct llcc_slice_config *llcc_table; Loading Loading @@ -358,14 +354,6 @@ static void qcom_llcc_cfg_program(struct platform_device *pdev) regmap_write(drv->llcc_map, attr1_cfg, attr1_val); regmap_write(drv->llcc_map, attr0_cfg, attr0_val); /* Write the retain on power collapse bit for each scid */ pcb |= llcc_table[i].retain_on_pc << llcc_table[i].slice_id; regmap_write(drv->llcc_map, LLCC_TRP_PCB_ACT, pcb); /* Disable capacity alloc */ cad |= llcc_table[i].dis_cap_alloc << llcc_table[i].slice_id; regmap_write(drv->llcc_map, LLCC_TRP_SCID_DIS_CAP_ALLOC, cad); /* Make sure that the SCT is programmed before activating */ mb(); Loading