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Commit d9aaf1dc authored by Andi Shyti's avatar Andi Shyti Committed by Mark Brown
Browse files

spi: s3c64xx: do not disable the clock while configuring the spi 



When the clock is coming from the cmu it is not required to be
disabled and then re-enabled in order to change the rate.

Besides, some exynos chipsets (e.g. exynos5433) do not deliver
any to the SFR if one from the pclk ("spi" in this case) or sclk
("busclk") is disabled.

Remove the clock disabling/enabling to avoid falling into this
situation.

Signed-off-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: default avatarAndi Shyti <andi.shyti@samsung.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 47c169ee

drivers/spi/spi-s3c64xx.c

+1 −7
Original line number Diff line number Diff line
@@ -596,9 +596,7 @@ static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) 
	u32 val;



	/* Disable Clock */

	if (sdd->port_conf->clk_from_cmu) {

		clk_disable_unprepare(sdd->src_clk);

	} else {

	if (!sdd->port_conf->clk_from_cmu) {

		val = readl(regs + S3C64XX_SPI_CLK_CFG);

		val &= ~S3C64XX_SPI_ENCLK_ENABLE;

		writel(val, regs + S3C64XX_SPI_CLK_CFG);
@@ -641,11 +639,7 @@ static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) 
	writel(val, regs + S3C64XX_SPI_MODE_CFG);



	if (sdd->port_conf->clk_from_cmu) {

		/* Configure Clock */

		/* There is half-multiplier before the SPI */

		clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);

		/* Enable Clock */

		clk_prepare_enable(sdd->src_clk);

	} else {

		/* Configure Clock */

		val = readl(regs + S3C64XX_SPI_CLK_CFG);