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Commit d93fbce9 authored by Lina Iyer's avatar Lina Iyer Committed by Gerrit - the friendly Code Review server
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drivers: soc: rpmh: Set up next wakeup correctly 



The wakeup value for the system is a tick value based on global timer
for the expected wakeup. Idle drivers provide the sleep interval in
usec. Convert that to a global timer tick and set that with the RPMH
block.

Setup the wakeup value on the hidden TCS with the higher order bytes in
Data0 and low order bytes in Data1. Also simplify writing the data into
the registers.

Change-Id: I2e6dde0382d4eea47e45723f273889c32408baa7
Signed-off-by: default avatarLina Iyer <ilina@codeaurora.org>
parent 50614cec

drivers/mailbox/qti-tcs.c

+3 −7
Original line number Diff line number Diff line
@@ -79,7 +79,6 @@ 


/* Control/Hidden TCS */

#define TCS_HIDDEN_MAX_SLOTS		3

#define TCS_HIDDEN_CMD0_DRV_ADDR	0x34

#define TCS_HIDDEN_CMD0_DRV_DATA	0x38

#define TCS_HIDDEN_CMD_SHIFT		0x08
@@ -830,15 +829,12 @@ static int tcs_mbox_invalidate(struct mbox_chan *chan) 
static void __tcs_write_hidden(void *base, int d, struct tcs_mbox_msg *msg)

{

	int i;

	void __iomem *addr;

	const u32 offset = TCS_HIDDEN_CMD0_DRV_DATA - TCS_HIDDEN_CMD0_DRV_ADDR;

	void __iomem *addr = base + TCS_HIDDEN_CMD0_DRV_DATA;



	addr = base + TCS_HIDDEN_CMD0_DRV_ADDR;

	for (i = 0; i < msg->num_payload; i++) {

		/* Only data is write capable */

		writel_relaxed(cpu_to_le32(msg->payload[i].data),

							addr + offset);

		trace_rpmh_control_msg(addr + offset, msg->payload[i].data);

		writel_relaxed(cpu_to_le32(msg->payload[i].data), addr);

		trace_rpmh_control_msg(addr, msg->payload[i].data);

		addr += TCS_HIDDEN_CMD_SHIFT;

	}

}

drivers/soc/qcom/system_pm.c

+14 −5
Original line number Diff line number Diff line 
/* Copyright (c) 2016, The Linux Foundation. All rights reserved.

/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -16,6 +16,7 @@ 


#include <soc/qcom/rpmh.h>



#define ARCH_TIMER_HZ		(19200000UL)

#define PDC_TIME_VALID_SHIFT	31

#define PDC_TIME_UPPER_MASK	0xFFFFFF
@@ -25,9 +26,9 @@ static int setup_wakeup(uint64_t sleep_val) 
{

	struct tcs_cmd cmd[3] = { { 0 } };



	cmd[0].data = sleep_val & 0xFFFFFFFF;

	cmd[1].data = (sleep_val >> 32) & PDC_TIME_UPPER_MASK;

	cmd[1].data |= 1 << PDC_TIME_VALID_SHIFT;

	cmd[0].data = (sleep_val >> 32) & PDC_TIME_UPPER_MASK;

	cmd[0].data |= 1 << PDC_TIME_VALID_SHIFT;

	cmd[1].data = sleep_val & 0xFFFFFFFF;



	return rpmh_write_control(rpmh_client, cmd, ARRAY_SIZE(cmd));

}
@@ -35,7 +36,7 @@ static int setup_wakeup(uint64_t sleep_val) 
/**

 * system_sleep_enter() - Activties done when entering system low power modes

 *

 * @sleep_val: The qtimer value for the next wakeup time

 * @sleep_val: The sleep duration in us.

 *

 * Returns 0 for success or error values from writing the timer value in the

 * hardware block.
@@ -51,6 +52,14 @@ int system_sleep_enter(uint64_t sleep_val) 
	if (ret)

		return ret;



	/*

	 * Set up the wake up value offset from the current time.

	 * Convert us to ns to allow div by 19.2 Mhz tick timer.

	 */

	sleep_val *= NSEC_PER_USEC;

	do_div(sleep_val, NSEC_PER_SEC/ARCH_TIMER_HZ);

	sleep_val += arch_counter_get_cntvct();



	return setup_wakeup(sleep_val);

}

EXPORT_SYMBOL(system_sleep_enter);