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Commit d920ec74 authored by Jeykumar Sankaran's avatar Jeykumar Sankaran Committed by Gerrit - the friendly Code Review server
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drm/msm/sde: avoid reprogramming display pipeline with continuous splash 



Bootloader does interface programming and basic display pipeline setup
while enabling continuous splash. Reprogramming some of those single
buffer registers may drive the hardware to a bad state. This change
avoids reprogramming those registers while handing off on first commit.

Change-Id: I9f24e0a3276998feea98322a256c216161c35eb8
Signed-off-by: default avatarJeykumar Sankaran <jsanka@codeaurora.org>
parent 74d7c38c

drivers/gpu/drm/msm/sde/sde_encoder.c

+10 −4
Original line number Diff line number Diff line
@@ -3436,16 +3436,21 @@ int sde_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc, 
{

	struct sde_encoder_virt *sde_enc;

	struct sde_encoder_phys *phys;

	struct sde_kms *sde_kms = NULL;

	struct msm_drm_private *priv = NULL;

	bool needs_hw_reset = false;

	uint32_t ln_cnt1, ln_cnt2;

	unsigned int i;

	int rc, ret = 0;



	if (!drm_enc || !params) {

	if (!drm_enc || !params || !drm_enc->dev ||

		!drm_enc->dev->dev_private) {

		SDE_ERROR("invalid args\n");

		return -EINVAL;

	}

	sde_enc = to_sde_encoder_virt(drm_enc);

	priv = drm_enc->dev->dev_private;

	sde_kms = to_sde_kms(priv->kms);



	SDE_DEBUG_ENC(sde_enc, "\n");

	SDE_EVT32(DRMID(drm_enc));
@@ -3514,7 +3519,8 @@ int sde_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc, 
		}

	}



	if (_sde_encoder_is_dsc_enabled(drm_enc)) {

	if (_sde_encoder_is_dsc_enabled(drm_enc) &&

		!sde_kms->splash_data.cont_splash_en) {

		rc = _sde_encoder_dsc_setup(sde_enc, params);

		if (rc) {

			SDE_ERROR_ENC(sde_enc, "failed to setup DSC: %d\n", rc);
@@ -4381,8 +4387,8 @@ int sde_encoder_update_caps_for_cont_splash(struct drm_encoder *encoder) 
		return ret;

	}



	if (conn->encoder) {

		conn->state->best_encoder = conn->encoder;

	if (sde_conn->encoder) {

		conn->state->best_encoder = sde_conn->encoder;

		SDE_DEBUG_ENC(sde_enc,

			"configured cstate->best_encoder to ID = %d\n",

			conn->state->best_encoder->base.id);

drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c

+2 −1
Original line number Diff line number Diff line
@@ -891,6 +891,7 @@ static void sde_encoder_phys_cmd_enable(struct sde_encoder_phys *phys_enc) 
	SDE_DEBUG_CMDENC(cmd_enc, "pp %d\n", phys_enc->hw_pp->idx - PINGPONG_0);



	if (phys_enc->enable_state == SDE_ENC_ENABLED) {

		if (!phys_enc->sde_kms->splash_data.cont_splash_en)

			SDE_ERROR("already enabled\n");

		return;

	}

drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c

+38 −14
Original line number Diff line number Diff line
@@ -263,7 +263,8 @@ static void programmable_rot_fetch_config(struct sde_encoder_phys *phys_enc, 
	if (!phys_enc || !vid_enc->hw_intf || !phys_enc->hw_ctl ||

			!phys_enc->hw_ctl->ops.get_bitmask_intf ||

			!phys_enc->hw_ctl->ops.update_pending_flush ||

			!vid_enc->hw_intf->ops.setup_rot_start)

			!vid_enc->hw_intf->ops.setup_rot_start ||

			!phys_enc->sde_kms)

		return;



	timing = &vid_enc->timing_params;
@@ -290,14 +291,17 @@ static void programmable_rot_fetch_config(struct sde_encoder_phys *phys_enc, 
		rot_fetch_lines, vfp_fetch_lines,

		rot_fetch_start_vsync_counter);



	if (!phys_enc->sde_kms->splash_data.cont_splash_en) {

		phys_enc->hw_ctl->ops.get_bitmask_intf(

			phys_enc->hw_ctl, &flush_mask, vid_enc->hw_intf->idx);

				phys_enc->hw_ctl, &flush_mask,

				vid_enc->hw_intf->idx);

		phys_enc->hw_ctl->ops.update_pending_flush(

				phys_enc->hw_ctl, flush_mask);



		spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);

		vid_enc->hw_intf->ops.setup_rot_start(vid_enc->hw_intf, &f);

		spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);

	}



	vid_enc->rot_fetch = f;

	vid_enc->rot_fetch_valid = true;
@@ -328,7 +332,8 @@ static void sde_encoder_phys_vid_setup_timing_engine( 
	unsigned long lock_flags;

	struct sde_hw_intf_cfg intf_cfg = { 0 };



	if (!phys_enc || !phys_enc->hw_ctl->ops.setup_intf_cfg) {

	if (!phys_enc || !phys_enc->sde_kms || !phys_enc->hw_ctl ||

			!phys_enc->hw_ctl->ops.setup_intf_cfg) {

		SDE_ERROR("invalid encoder %d\n", phys_enc != 0);

		return;

	}
@@ -358,6 +363,14 @@ static void sde_encoder_phys_vid_setup_timing_engine( 


	drm_mode_to_intf_timing_params(vid_enc, &mode, &timing_params);



	vid_enc->timing_params = timing_params;



	if (phys_enc->sde_kms->splash_data.cont_splash_en) {

		SDE_DEBUG_VIDENC(vid_enc,

			"skipping intf programming since cont splash is enabled\n");

		return;

	}



	fmt = sde_get_sde_format(fmt_fourcc);

	SDE_DEBUG_VIDENC(vid_enc, "fmt_fourcc 0x%X\n", fmt_fourcc);
@@ -371,10 +384,7 @@ static void sde_encoder_phys_vid_setup_timing_engine( 
			&timing_params, fmt);

	phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);

	spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);



	programmable_fetch_config(phys_enc, &timing_params);



	vid_enc->timing_params = timing_params;

}



static void sde_encoder_phys_vid_vblank_irq(void *arg, int irq_idx)
@@ -653,7 +663,8 @@ static void sde_encoder_phys_vid_enable(struct sde_encoder_phys *phys_enc) 
	u32 flush_mask = 0;



	if (!phys_enc || !phys_enc->parent || !phys_enc->parent->dev ||

			!phys_enc->parent->dev->dev_private) {

			!phys_enc->parent->dev->dev_private ||

			!phys_enc->sde_kms) {

		SDE_ERROR("invalid encoder/device\n");

		return;

	}
@@ -676,7 +687,9 @@ static void sde_encoder_phys_vid_enable(struct sde_encoder_phys *phys_enc) 
	/* reset state variables until after first update */

	vid_enc->rot_fetch_valid = false;



	sde_encoder_helper_split_config(phys_enc, vid_enc->hw_intf->idx);

	if (!phys_enc->sde_kms->splash_data.cont_splash_en)

		sde_encoder_helper_split_config(phys_enc,

						vid_enc->hw_intf->idx);



	sde_encoder_phys_vid_setup_timing_engine(phys_enc);
@@ -689,6 +702,17 @@ static void sde_encoder_phys_vid_enable(struct sde_encoder_phys *phys_enc) 
		!sde_encoder_phys_vid_is_master(phys_enc))

		goto skip_flush;



	/**

	 * skip flushing intf during cont. splash handoff since bootloader

	 * has already enabled the hardware and is single buffered.

	 */



	if (phys_enc->sde_kms->splash_data.cont_splash_en) {

		SDE_DEBUG_VIDENC(vid_enc,

		"skipping intf flush bit set as cont. splash is enabled\n");

		goto skip_flush;

	}



	ctl->ops.get_bitmask_intf(ctl, &flush_mask, intf->idx);

	ctl->ops.update_pending_flush(ctl, flush_mask);