Commit d90a9fb2 authored Nov 01, 2021 by Maxim Kiselev Committed by Greg Kroah-Hartman Nov 26, 2021

net: davinci_emac: Fix interrupt pacing disable



[ Upstream commit d52bcb47bdf971a59a2467975d2405fcfcb2fa19 ]

This patch allows to use 0 for `coal->rx_coalesce_usecs` param to
disable rx irq coalescing.

Previously we could enable rx irq coalescing via ethtool
(For ex: `ethtool -C eth0 rx-usecs 2000`) but we couldn't disable
it because this part rejects 0 value:

       if (!coal->rx_coalesce_usecs)
               return -EINVAL;

Fixes: 84da2658 ("TI DaVinci EMAC : Implement interrupt pacing functionality.")
Signed-off-by: Maxim Kiselev <bigunclemax@gmail.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Link: https://lore.kernel.org/r/20211101152343.4193233-1-bigunclemax@gmail.com


Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

parent 848b2123

drivers/net/ethernet/ti/davinci_emac.c

+14 −2

Original line number	Original line	Diff line number	Diff line
	@@ -426,8 +426,20 @@ static int emac_set_coalesce(struct net_device *ndev,
	u32 int_ctrl, num_interrupts = 0;		u32 int_ctrl, num_interrupts = 0;
	u32 prescale = 0, addnl_dvdr = 1, coal_intvl = 0;		u32 prescale = 0, addnl_dvdr = 1, coal_intvl = 0;

	if (!coal->rx_coalesce_usecs)		if (!coal->rx_coalesce_usecs) {
	return -EINVAL;		priv->coal_intvl = 0;

			switch (priv->version) {
			case EMAC_VERSION_2:
			emac_ctrl_write(EMAC_DM646X_CMINTCTRL, 0);
			break;
			default:
			emac_ctrl_write(EMAC_CTRL_EWINTTCNT, 0);
			break;
			}

			return 0;
			}

	coal_intvl = coal->rx_coalesce_usecs;		coal_intvl = coal->rx_coalesce_usecs;