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Commit d8e19f99 authored by Xiong Zhang's avatar Xiong Zhang Committed by Jani Nikula
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drm/i915/skl: Adding DDI_E power well domain 



From B spec, DDI_E port belong to PowerWell 2, but
DDI_E share the powerwell_req/staus register bit with
DDI_A which belong to DDI_A_E_POWER_WELL.

In order to communicate with the connector on DDI-E, both
DDI_A_E_POWER_WELL and POWER_WELL_2 must be enabled.

Currently intel_dp_power_get(DDI_E) only enable
DDI_A_E_POWER_WELL, this patch will not only enable
DDI_a_E_POWER_WELL but also enable POWER_WELL_2.

This patch also fix the DDI-E hotplug function.

Signed-off-by: default avatarXiong Zhang <xiong.y.zhang@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 477ec328

drivers/gpu/drm/i915/i915_debugfs.c

+2 −0
Original line number Diff line number Diff line
@@ -2562,6 +2562,8 @@ static const char *power_domain_str(enum intel_display_power_domain domain) 
		return "PORT_DDI_D_2_LANES";

	case POWER_DOMAIN_PORT_DDI_D_4_LANES:

		return "PORT_DDI_D_4_LANES";

	case POWER_DOMAIN_PORT_DDI_E_2_LANES:

		return "PORT_DDI_E_2_LANES";

	case POWER_DOMAIN_PORT_DSI:

		return "PORT_DSI";

	case POWER_DOMAIN_PORT_CRT:

drivers/gpu/drm/i915/i915_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -182,6 +182,7 @@ enum intel_display_power_domain { 
	POWER_DOMAIN_PORT_DDI_C_4_LANES,

	POWER_DOMAIN_PORT_DDI_D_2_LANES,

	POWER_DOMAIN_PORT_DDI_D_4_LANES,

	POWER_DOMAIN_PORT_DDI_E_2_LANES,

	POWER_DOMAIN_PORT_DSI,

	POWER_DOMAIN_PORT_CRT,

	POWER_DOMAIN_PORT_OTHER,

drivers/gpu/drm/i915/intel_display.c

+2 −1
Original line number Diff line number Diff line
@@ -5150,7 +5150,6 @@ static enum intel_display_power_domain port_to_power_domain(enum port port) 
{

	switch (port) {

	case PORT_A:

	case PORT_E:

		return POWER_DOMAIN_PORT_DDI_A_4_LANES;

	case PORT_B:

		return POWER_DOMAIN_PORT_DDI_B_4_LANES;
@@ -5158,6 +5157,8 @@ static enum intel_display_power_domain port_to_power_domain(enum port port) 
		return POWER_DOMAIN_PORT_DDI_C_4_LANES;

	case PORT_D:

		return POWER_DOMAIN_PORT_DDI_D_4_LANES;

	case PORT_E:

		return POWER_DOMAIN_PORT_DDI_E_2_LANES;

	default:

		WARN_ON_ONCE(1);

		return POWER_DOMAIN_PORT_OTHER;

drivers/gpu/drm/i915/intel_runtime_pm.c

+2 −0
Original line number Diff line number Diff line
@@ -297,6 +297,7 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv, 
	BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |		\

	BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |		\

	BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |		\

	BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) |		\

	BIT(POWER_DOMAIN_AUX_B) |                       \

	BIT(POWER_DOMAIN_AUX_C) |			\

	BIT(POWER_DOMAIN_AUX_D) |			\
@@ -316,6 +317,7 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv, 
#define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS (		\

	BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) |		\

	BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) |		\

	BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) |		\

	BIT(POWER_DOMAIN_INIT))

#define SKL_DISPLAY_DDI_B_POWER_DOMAINS (		\

	BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |		\