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Commit d8cacaa3 authored by Maxime Ripard's avatar Maxime Ripard
Browse files

ARM: sunxi: DT: Fix lines over 80 characters 



A few lines in our DTSIs are over the 80 characters limit, making
checkpatch complain about that.

If possible (and relevant), wrap these lines to 80 characters.

Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent c0c2eb24

arch/arm/boot/dts/sun4i-a10.dtsi

+8 −4
Original line number Diff line number Diff line
@@ -61,7 +61,8 @@ 
		ranges;



		framebuffer@0 {

			compatible = "allwinner,simple-framebuffer", "simple-framebuffer";

			compatible = "allwinner,simple-framebuffer",

				     "simple-framebuffer";

			allwinner,pipeline = "de_be0-lcd0-hdmi";

			clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,

				 <&ahb_gates 44>;
@@ -69,7 +70,8 @@ 
		};



		framebuffer@1 {

			compatible = "allwinner,simple-framebuffer", "simple-framebuffer";

			compatible = "allwinner,simple-framebuffer",

				     "simple-framebuffer";

			allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";

			clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,

				 <&ahb_gates 44>, <&ahb_gates 46>;
@@ -433,7 +435,8 @@ 
			compatible = "allwinner,sun4i-a10-usb-clk";

			reg = <0x01c200cc 0x4>;

			clocks = <&pll6 1>;

			clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";

			clock-output-names = "usb_ohci0", "usb_ohci1",

					     "usb_phy";

		};



		spi3_clk: clk@01c200d4 {
@@ -779,7 +782,8 @@ 
			};



			mmc0_pins_a: mmc0@0 {

				allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";

				allwinner,pins = "PF0", "PF1", "PF2",

						 "PF3", "PF4", "PF5";

				allwinner,function = "mmc0";

				allwinner,drive = <SUN4I_PINCTRL_30_MA>;

				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;

arch/arm/boot/dts/sun5i-a10s.dtsi

+18 −11
Original line number Diff line number Diff line
@@ -62,7 +62,8 @@ 
		ranges;



		framebuffer@0 {

			compatible = "allwinner,simple-framebuffer", "simple-framebuffer";

			compatible = "allwinner,simple-framebuffer",

				     "simple-framebuffer";

			allwinner,pipeline = "de_be0-lcd0-hdmi";

			clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,

				 <&ahb_gates 44>;
@@ -84,13 +85,17 @@ 
			compatible = "allwinner,sun5i-a10s-ahb-gates-clk";

			reg = <0x01c20060 0x8>;

			clocks = <&ahb>;

			clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",

				"ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",

				"ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",

				"ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",

				"ahb_spi2", "ahb_gps", "ahb_stimer", "ahb_ve",

				"ahb_tve", "ahb_lcd", "ahb_csi", "ahb_hdmi",

				"ahb_de_be", "ahb_de_fe", "ahb_iep", "ahb_mali400";

			clock-output-names = "ahb_usbotg", "ahb_ehci",

					     "ahb_ohci", "ahb_ss", "ahb_dma",

					     "ahb_bist", "ahb_mmc0", "ahb_mmc1",

					     "ahb_mmc2", "ahb_nand",

					     "ahb_sdram", "ahb_emac", "ahb_ts",

					     "ahb_spi0", "ahb_spi1", "ahb_spi2",

					     "ahb_gps", "ahb_stimer", "ahb_ve",

					     "ahb_tve", "ahb_lcd", "ahb_csi",

					     "ahb_hdmi", "ahb_de_be",

					     "ahb_de_fe", "ahb_iep",

					     "ahb_mali400";

		};



		apb0_gates: clk@01c20068 {
@@ -98,8 +103,9 @@ 
			compatible = "allwinner,sun5i-a10s-apb0-gates-clk";

			reg = <0x01c20068 0x4>;

			clocks = <&apb0>;

			clock-output-names = "apb0_codec", "apb0_iis", "apb0_pio",

				"apb0_ir", "apb0_keypad";

			clock-output-names = "apb0_codec", "apb0_iis",

					     "apb0_pio", "apb0_ir",

					     "apb0_keypad";

		};



		apb1_gates: clk@01c2006c {
@@ -188,7 +194,8 @@ 
	};



	mmc1_pins_a: mmc1@0 {

		allwinner,pins = "PG3","PG4","PG5","PG6","PG7","PG8";

		allwinner,pins = "PG3", "PG4", "PG5",

				 "PG6", "PG7", "PG8";

		allwinner,function = "mmc1";

		allwinner,drive = <SUN4I_PINCTRL_30_MA>;

		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;

arch/arm/boot/dts/sun5i-a13.dtsi

+12 −7
Original line number Diff line number Diff line
@@ -104,12 +104,16 @@ 
			compatible = "allwinner,sun5i-a13-ahb-gates-clk";

			reg = <0x01c20060 0x8>;

			clocks = <&ahb>;

			clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",

				"ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",

				"ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",

				"ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_stimer",

				"ahb_ve", "ahb_lcd", "ahb_csi", "ahb_de_be",

				"ahb_de_fe", "ahb_iep", "ahb_mali400";

			clock-output-names = "ahb_usbotg", "ahb_ehci",

					     "ahb_ohci", "ahb_ss", "ahb_dma",

					     "ahb_bist", "ahb_mmc0", "ahb_mmc1",

					     "ahb_mmc2", "ahb_nand",

					     "ahb_sdram", "ahb_spi0",

					     "ahb_spi1", "ahb_spi2",

					     "ahb_stimer", "ahb_ve", "ahb_lcd",

					     "ahb_csi", "ahb_de_be",

					     "ahb_de_fe", "ahb_iep",

					     "ahb_mali400";

		};



		apb0_gates: clk@01c20068 {
@@ -117,7 +121,8 @@ 
			compatible = "allwinner,sun5i-a13-apb0-gates-clk";

			reg = <0x01c20068 0x4>;

			clocks = <&apb0>;

			clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";

			clock-output-names = "apb0_codec", "apb0_pio",

					     "apb0_ir";

		};



		apb1_gates: clk@01c2006c {

arch/arm/boot/dts/sun5i.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -505,7 +505,8 @@ 
			};



			mmc0_pins_a: mmc0@0 {

				allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";

				allwinner,pins = "PF0", "PF1", "PF2", "PF3",

						 "PF4", "PF5";

				allwinner,function = "mmc0";

				allwinner,drive = <SUN4I_PINCTRL_30_MA>;

				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;

arch/arm/boot/dts/sun6i-a31.dtsi

+19 −11
Original line number Diff line number Diff line
@@ -62,7 +62,8 @@ 
		ranges;



		framebuffer@0 {

			compatible = "allwinner,simple-framebuffer", "simple-framebuffer";

			compatible = "allwinner,simple-framebuffer",

				     "simple-framebuffer";

			allwinner,pipeline = "de_be0-lcd0-hdmi";

			clocks = <&pll6 0>;

			status = "disabled";
@@ -299,8 +300,9 @@ 
			reg = <0x01c2006c 0x4>;

			clocks = <&apb2>;

			clock-output-names = "apb2_i2c0", "apb2_i2c1",

					"apb2_i2c2", "apb2_i2c3", "apb2_uart0",

					"apb2_uart1", "apb2_uart2", "apb2_uart3",

					     "apb2_i2c2", "apb2_i2c3",

					     "apb2_uart0", "apb2_uart1",

					     "apb2_uart2", "apb2_uart3",

					     "apb2_uart4", "apb2_uart5";

		};
@@ -388,10 +390,13 @@ 
		};



		/*

		 * The following two are dummy clocks, placeholders used in the gmac_tx

		 * clock. The gmac driver will choose one parent depending on the PHY

		 * interface mode, using clk_set_rate auto-reparenting.

		 * The actual TX clock rate is not controlled by the gmac_tx clock.

		 * The following two are dummy clocks, placeholders

		 * used in the gmac_tx clock. The gmac driver will

		 * choose one parent depending on the PHY interface

		 * mode, using clk_set_rate auto-reparenting.

		 *

		 * The actual TX clock rate is not controlled by the

		 * gmac_tx clock.

		 */

		mii_phy_tx_clk: clk@1 {

			#clock-cells = <0>;
@@ -627,7 +632,8 @@ 
			};



			mmc0_pins_a: mmc0@0 {

				allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";

				allwinner,pins = "PF0", "PF1", "PF2",

						 "PF3", "PF4", "PF5";

				allwinner,function = "mmc0";

				allwinner,drive = <SUN4I_PINCTRL_30_MA>;

				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
@@ -865,7 +871,8 @@ 
		};



		timer@01c60000 {

			compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer";

			compatible = "allwinner,sun6i-a31-hstimer",

				     "allwinner,sun7i-a20-hstimer";

			reg = <0x01c60000 0x1000>;

			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
@@ -956,7 +963,8 @@ 
			ar100: ar100_clk {

				compatible = "allwinner,sun6i-a31-ar100-clk";

				#clock-cells = <0>;

				clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;

				clocks = <&osc32k>, <&osc24M>, <&pll6 0>,

					 <&pll6 0>;

				clock-output-names = "ar100";

			};