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Commit d874bcff authored by Jesse Barnes's avatar Jesse Barnes Committed by Eric Anholt
Browse files

drm/i915: remove duplicate PIPE*STAT bit definitions 



Having two sets has made me think I caught a bug more than once now.

Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarEric Anholt <eric@anholt.net>
parent e25e6601

drivers/gpu/drm/i915/i915_irq.c

+6 −6
Original line number Diff line number Diff line
@@ -171,10 +171,10 @@ void intel_enable_asle (struct drm_device *dev) 
		ironlake_enable_display_irq(dev_priv, DE_GSE);

	else {

		i915_enable_pipestat(dev_priv, 1,

				     I915_LEGACY_BLC_EVENT_ENABLE);

				     PIPE_LEGACY_BLC_EVENT_ENABLE);

		if (IS_I965G(dev))

			i915_enable_pipestat(dev_priv, 0,

					     I915_LEGACY_BLC_EVENT_ENABLE);

					     PIPE_LEGACY_BLC_EVENT_ENABLE);

	}

}
@@ -856,9 +856,9 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) 
	iir = I915_READ(IIR);



	if (IS_I965G(dev))

		vblank_status = I915_START_VBLANK_INTERRUPT_STATUS;

		vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;

	else

		vblank_status = I915_VBLANK_INTERRUPT_STATUS;

		vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;



	for (;;) {

		irq_received = iir != 0;
@@ -962,8 +962,8 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) 
				intel_finish_page_flip(dev, 1);

		}



		if ((pipea_stats & I915_LEGACY_BLC_EVENT_STATUS) ||

		    (pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) ||

		if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||

		    (pipeb_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||

		    (iir & I915_ASLE_INTERRUPT))

			opregion_asle_intr(dev);

drivers/gpu/drm/i915/i915_reg.h

+0 −26
Original line number Diff line number Diff line
@@ -595,32 +595,6 @@ 
#define   DPLL_FPA01_P1_POST_DIV_MASK	0x00ff0000 /* i915 */

#define   DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW	0x00ff8000 /* Pineview */



#define I915_FIFO_UNDERRUN_STATUS		(1UL<<31)

#define I915_CRC_ERROR_ENABLE			(1UL<<29)

#define I915_CRC_DONE_ENABLE			(1UL<<28)

#define I915_GMBUS_EVENT_ENABLE			(1UL<<27)

#define I915_VSYNC_INTERRUPT_ENABLE		(1UL<<25)

#define I915_DISPLAY_LINE_COMPARE_ENABLE	(1UL<<24)

#define I915_DPST_EVENT_ENABLE			(1UL<<23)

#define I915_LEGACY_BLC_EVENT_ENABLE		(1UL<<22)

#define I915_ODD_FIELD_INTERRUPT_ENABLE		(1UL<<21)

#define I915_EVEN_FIELD_INTERRUPT_ENABLE	(1UL<<20)

#define I915_START_VBLANK_INTERRUPT_ENABLE	(1UL<<18)	/* 965 or later */

#define I915_VBLANK_INTERRUPT_ENABLE		(1UL<<17)

#define I915_OVERLAY_UPDATED_ENABLE		(1UL<<16)

#define I915_CRC_ERROR_INTERRUPT_STATUS		(1UL<<13)

#define I915_CRC_DONE_INTERRUPT_STATUS		(1UL<<12)

#define I915_GMBUS_INTERRUPT_STATUS		(1UL<<11)

#define I915_VSYNC_INTERRUPT_STATUS		(1UL<<9)

#define I915_DISPLAY_LINE_COMPARE_STATUS	(1UL<<8)

#define I915_DPST_EVENT_STATUS			(1UL<<7)

#define I915_LEGACY_BLC_EVENT_STATUS		(1UL<<6)

#define I915_ODD_FIELD_INTERRUPT_STATUS		(1UL<<5)

#define I915_EVEN_FIELD_INTERRUPT_STATUS	(1UL<<4)

#define I915_START_VBLANK_INTERRUPT_STATUS	(1UL<<2)	/* 965 or later */

#define I915_VBLANK_INTERRUPT_STATUS		(1UL<<1)

#define I915_OVERLAY_UPDATED_STATUS		(1UL<<0)



#define SRX_INDEX		0x3c4

#define SRX_DATA		0x3c5

#define SR01			1