Merge "msm: kgsl: Dump GMU snapshot" (d81d1be0) · Commits · e / devices / android_kernel_fairphone_FP3

drivers/gpu/msm/a6xx_reg.h

+1 −0

Original line number	Original line	Diff line number	Diff line
	@@ -941,6 +941,7 @@

	/* GPUCC registers */		/* GPUCC registers */
	#define A6XX_GPU_CC_GX_GDSCR 0x24403		#define A6XX_GPU_CC_GX_GDSCR 0x24403
			#define A6XX_GPU_CC_GX_DOMAIN_MISC 0x24542

	/* GPU RSC sequencer registers */		/* GPU RSC sequencer registers */
	#define A6XX_RSCC_PDC_SEQ_START_ADDR 0x23408		#define A6XX_RSCC_PDC_SEQ_START_ADDR 0x23408

+2 −0

Original line number	Original line	Diff line number	Diff line
	@@ -642,6 +642,8 @@ enum adreno_regs {
	ADRENO_REG_GMU_HOST2GMU_INTR_SET,		ADRENO_REG_GMU_HOST2GMU_INTR_SET,
	ADRENO_REG_GMU_HOST2GMU_INTR_CLR,		ADRENO_REG_GMU_HOST2GMU_INTR_CLR,
	ADRENO_REG_GMU_HOST2GMU_INTR_RAW_INFO,		ADRENO_REG_GMU_HOST2GMU_INTR_RAW_INFO,
			ADRENO_REG_GMU_NMI_CONTROL_STATUS,
			ADRENO_REG_GMU_CM3_CFG,
	ADRENO_REG_GPMU_POWER_COUNTER_ENABLE,		ADRENO_REG_GPMU_POWER_COUNTER_ENABLE,
	ADRENO_REG_REGISTER_MAX,		ADRENO_REG_REGISTER_MAX,
	};		};

+8 −0

Original line number	Original line	Diff line number	Diff line
	@@ -1289,6 +1289,10 @@ static int a6xx_rpmh_power_on_gpu(struct kgsl_device *device)
	{		{
	struct gmu_device *gmu = &device->gmu;		struct gmu_device *gmu = &device->gmu;
	struct device *dev = &gmu->pdev->dev;		struct device *dev = &gmu->pdev->dev;
			int val;

			kgsl_gmu_regread(device, A6XX_GPU_CC_GX_DOMAIN_MISC, &val);
			WARN_ON(!(val & 0x1));

	/* RSC wake sequence */		/* RSC wake sequence */
	kgsl_gmu_regwrite(device, A6XX_GMU_RSCC_CONTROL_REQ, BIT(1));		kgsl_gmu_regwrite(device, A6XX_GMU_RSCC_CONTROL_REQ, BIT(1));
	@@ -2770,6 +2774,10 @@ static unsigned int a6xx_register_offsets[ADRENO_REG_REGISTER_MAX] = {
	A6XX_GMU_HOST2GMU_INTR_CLR),		A6XX_GMU_HOST2GMU_INTR_CLR),
	ADRENO_REG_DEFINE(ADRENO_REG_GMU_HOST2GMU_INTR_RAW_INFO,		ADRENO_REG_DEFINE(ADRENO_REG_GMU_HOST2GMU_INTR_RAW_INFO,
	A6XX_GMU_HOST2GMU_INTR_RAW_INFO),		A6XX_GMU_HOST2GMU_INTR_RAW_INFO),
			ADRENO_REG_DEFINE(ADRENO_REG_GMU_NMI_CONTROL_STATUS,
			A6XX_GMU_NMI_CONTROL_STATUS),
			ADRENO_REG_DEFINE(ADRENO_REG_GMU_CM3_CFG,
			A6XX_GMU_CM3_CFG),
	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_SECVID_TRUST_CONTROL,		ADRENO_REG_DEFINE(ADRENO_REG_RBBM_SECVID_TRUST_CONTROL,
	A6XX_RBBM_SECVID_TRUST_CNTL),		A6XX_RBBM_SECVID_TRUST_CNTL),
	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_BASE,		ADRENO_REG_DEFINE(ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_BASE,

+3 −3

Original line number	Original line	Diff line number	Diff line
	@@ -231,9 +231,9 @@ static const unsigned int a6xx_gmu_registers[] = {
	0x1F980, 0x1F986, 0x1F990, 0x1F99E, 0x1F9C0, 0x1F9C0, 0x1F9C5, 0x1F9CC,		0x1F980, 0x1F986, 0x1F990, 0x1F99E, 0x1F9C0, 0x1F9C0, 0x1F9C5, 0x1F9CC,
	0x1F9E0, 0x1F9E2, 0x1F9F0, 0x1F9F0, 0x1FA00, 0x1FA03,		0x1F9E0, 0x1F9E2, 0x1F9F0, 0x1F9F0, 0x1FA00, 0x1FA03,
	/* GPU RSCC */		/* GPU RSCC */
	0x23740, 0x23742, 0x23744, 0x23747, 0x2374C, 0x23787, 0x237EC, 0x237EF,		0x2348C, 0x2348C, 0x23501, 0x23502, 0x23740, 0x23742, 0x23744, 0x23747,
	0x237F4, 0x2382F, 0x23894, 0x23897, 0x2389C, 0x238D7, 0x2393C, 0x2393F,		0x2374C, 0x23787, 0x237EC, 0x237EF, 0x237F4, 0x2382F, 0x23894, 0x23897,
	0x23944, 0x2397F,		0x2389C, 0x238D7, 0x2393C, 0x2393F, 0x23944, 0x2397F,
	/* GMU AO */		/* GMU AO */
	0x23B00, 0x23B16, 0x23C00, 0x23C00,		0x23B00, 0x23B16, 0x23C00, 0x23C00,
	/* GPU CC */		/* GPU CC */

+5 −0

Original line number	Original line	Diff line number	Diff line
	@@ -669,9 +669,14 @@ static inline struct kgsl_device kgsl_device_from_dev(struct device dev)

	static inline int kgsl_state_is_awake(struct kgsl_device *device)		static inline int kgsl_state_is_awake(struct kgsl_device *device)
	{		{
			struct gmu_device *gmu = &device->gmu;

	if (device->state == KGSL_STATE_ACTIVE \|\|		if (device->state == KGSL_STATE_ACTIVE \|\|
	device->state == KGSL_STATE_AWARE)		device->state == KGSL_STATE_AWARE)
	return true;		return true;
			else if (kgsl_gmu_isenabled(device) &&
			test_bit(GMU_CLK_ON, &gmu->flags))
			return true;
	else		else
	return false;		return false;
	}		}