Merge "drm/msm: Expose Assertive display capability" into msm-4.8 (d81c0e5f) · Commits · e / devices / android_kernel_fairphone_FP3

drivers/gpu/drm/msm/sde/sde_color_processing.c

+49 −2

Original line number	Diff line number	Diff line
		@@ -61,6 +61,7 @@ enum {
		SDE_CP_CRTC_DSPP_GAMUT,
		SDE_CP_CRTC_DSPP_DITHER,
		SDE_CP_CRTC_DSPP_HIST,
		SDE_CP_CRTC_DSPP_AD,
		SDE_CP_CRTC_DSPP_MAX,
		/* DSPP features end */

		@@ -72,14 +73,14 @@ enum {
		SDE_CP_CRTC_MAX_FEATURES,
		};

		#define INIT_PROP_ATTACH(p, crtc, prop, node, blk, feature, ops, val) \
		#define INIT_PROP_ATTACH(p, crtc, prop, node, blk, feature, func, val) \
		do { \
		(p)->crtc = crtc; \
		(p)->prop = prop; \
		(p)->prop_node = node; \
		(p)->pp_blk = blk; \
		(p)->feature = feature; \
		(p)->ops = ops; \
		(p)->ops = func; \
		(p)->val = val; \
		} while (0)

		@@ -209,6 +210,45 @@ void sde_cp_crtc_init(struct drm_crtc *crtc)
		INIT_LIST_HEAD(&sde_crtc->feature_list);
		}

		static void sde_cp_crtc_install_immutable_property(struct drm_crtc *crtc,
		char *name,
		u32 feature)
		{
		struct drm_property *prop;
		struct sde_color_process_node *prop_node = NULL;
		struct msm_drm_private *priv;
		struct sde_cp_prop_attach prop_attach;
		uint64_t val = 0;

		if (feature >= SDE_CP_CRTC_MAX_FEATURES) {
		DRM_ERROR("invalid feature %d max %d\n", feature,
		SDE_CP_CRTC_MAX_FEATURES);
		return;
		}

		prop_node = kzalloc(sizeof(*prop_node), GFP_KERNEL);
		if (!prop_node)
		return;

		priv = crtc->dev->dev_private;
		prop = priv->cp_property[feature];

		if (!prop) {
		prop = drm_property_create(crtc->dev, DRM_MODE_PROP_IMMUTABLE,
		name, 0);
		if (!prop) {
		DRM_ERROR("property create failed: %s\n", name);
		kfree(prop_node);
		return;
		}
		priv->cp_property[feature] = prop;
		}

		INIT_PROP_ATTACH(&prop_attach, crtc, prop, prop_node, NULL,
		feature, NULL, val);
		sde_cp_crtc_prop_attach(&prop_attach);
		}

		static void sde_cp_crtc_install_range_property(struct drm_crtc *crtc,
		char *name,
		const struct sde_pp_blk *pp_blk,
		@@ -502,6 +542,13 @@ void sde_cp_crtc_install_properties(struct drm_crtc *crtc)
		SDE_CP_CRTC_DSPP_HUE, hw_dspp->ops.setup_hue,
		0, U32_MAX, 0);
		break;
		case SDE_DSPP_AD:
		snprintf(feature_name, ARRAY_SIZE(feature_name), "%s%d",
		"SDE_DSPP_AD_V",
		(hw_dspp->cap->sblk->ad.version >> 16));
		sde_cp_crtc_install_immutable_property(crtc,
		feature_name, SDE_CP_CRTC_DSPP_AD);
		break;
		default:
		break;
		}

drivers/gpu/drm/msm/sde/sde_hw_catalog.h

+2 −13

Original line number	Diff line number	Diff line
		@@ -140,6 +140,7 @@ enum {
		SDE_DSPP_GAMUT,
		SDE_DSPP_DITHER,
		SDE_DSPP_HIST,
		SDE_DSPP_AD,
		SDE_DSPP_MAX
		};

		@@ -356,6 +357,7 @@ struct sde_dspp_sub_blks {
		struct sde_pp_blk gamut;
		struct sde_pp_blk dither;
		struct sde_pp_blk hist;
		struct sde_pp_blk ad;
		};

		struct sde_pingpong_sub_blks {
		@@ -536,16 +538,6 @@ struct sde_wb_cfg {
		enum sde_clk_ctrl_type clk_ctrl;
		};

		/**
		* struct sde_ad_cfg - information of Assertive Display blocks
		* @id enum identifying this block
		* @base register offset of this block
		* @features bit mask identifying sub-blocks/features
		*/
		struct sde_ad_cfg {
		SDE_HW_BLK_INFO;
		};

		/**
		* struct sde_vbif_dynamic_ot_cfg - dynamic OT setting
		* @pps pixel per seconds
		@@ -626,9 +618,6 @@ struct sde_mdss_cfg {
		u32 wb_count;
		struct sde_wb_cfg wb[MAX_BLOCKS];

		u32 ad_count;
		struct sde_ad_cfg ad[MAX_BLOCKS];

		u32 vbif_count;
		struct sde_vbif_cfg vbif[MAX_BLOCKS];
		/* Add additional block data structures here */

drivers/gpu/drm/msm/sde/sde_hw_catalog_8996.c

+4 −7

Original line number	Diff line number	Diff line
		@@ -41,7 +41,7 @@
		(BIT(SDE_DSPP_IGC) \| BIT(SDE_DSPP_PCC) \|\
		BIT(SDE_DSPP_GC) \| BIT(SDE_DSPP_HSIC) \| BIT(SDE_DSPP_GAMUT) \|\
		BIT(SDE_DSPP_DITHER) \| BIT(SDE_DSPP_HIST) \| BIT(SDE_DSPP_MEMCOLOR) \|\
		BIT(SDE_DSPP_SIXZONE))
		BIT(SDE_DSPP_SIXZONE) \| BIT(SDE_DSPP_AD))

		#define PINGPONG_17X_MASK \
		(BIT(SDE_PINGPONG_TE) \| BIT(SDE_PINGPONG_DSC))
		@@ -344,7 +344,7 @@ static inline int set_cfg_1xx_init(struct sde_mdss_cfg *cfg)
		static const struct sde_dspp_sub_blks dspp = {
		.igc = {.id = SDE_DSPP_IGC, .base = 0x0, .len = 0x0,
		.version = SDE_COLOR_PROCESS_VER(0x1, 0x0)},
		.pcc = {.id = SDE_DSPP_PCC, .base = 0x0, .len = 0x7,
		.pcc = {.id = SDE_DSPP_PCC, .base = 0x0, .len = 0x0,
		.version = SDE_COLOR_PROCESS_VER(0x1, 0x0)},
		.gamut = {.id = SDE_DSPP_GAMUT, .base = 0x0, .len = 0x0,
		.version = SDE_COLOR_PROCESS_VER(0x1, 0x0)},
		@@ -360,6 +360,8 @@ static inline int set_cfg_1xx_init(struct sde_mdss_cfg *cfg)
		.version = SDE_COLOR_PROCESS_VER(0x1, 0x0)},
		.gc = {.id = SDE_DSPP_GC, .base = 0x0, .len = 0x0,
		.version = SDE_COLOR_PROCESS_VER(0x1, 0x0)},
		.ad = {.id = SDE_DSPP_AD, .base = 0x00, .len = 0x0,
		.version = SDE_COLOR_PROCESS_VER(0x3, 0x0)},
		};

		/* PINGPONG capability */
		@@ -607,11 +609,6 @@ static inline int set_cfg_1xx_init(struct sde_mdss_cfg *cfg)
		.xin_id = 6,
		.clk_ctrl = SDE_CLK_CTRL_WB2},
		},
		.ad_count = 2,
		.ad = {
		{.id = AD_0, .base = 0x00079000},
		{.id = AD_1, .base = 0x00079800},
		},
		.vbif_count = 2,
		.vbif = {
		{.id = VBIF_0,