Loading drivers/gpu/drm/msm/sde/sde_color_processing.c +1 −1 Original line number Original line Diff line number Diff line Loading @@ -1164,7 +1164,7 @@ static void dspp_ad_install_property(struct drm_crtc *crtc) sde_cp_create_local_blob(crtc, SDE_CP_CRTC_DSPP_AD_CFG, sde_cp_create_local_blob(crtc, SDE_CP_CRTC_DSPP_AD_CFG, sizeof(struct drm_msm_ad4_cfg)); sizeof(struct drm_msm_ad4_cfg)); sde_cp_crtc_install_range_property(crtc, sde_cp_crtc_install_range_property(crtc, "SDE_DSPP_AD_V4_ASSERTIVNESS", "SDE_DSPP_AD_V4_ASSERTIVENESS", SDE_CP_CRTC_DSPP_AD_ASSERTIVENESS, 0, (BIT(8) - 1), 0); SDE_CP_CRTC_DSPP_AD_ASSERTIVENESS, 0, (BIT(8) - 1), 0); sde_cp_crtc_install_range_property(crtc, "SDE_DSPP_AD_V4_INPUT", sde_cp_crtc_install_range_property(crtc, "SDE_DSPP_AD_V4_INPUT", SDE_CP_CRTC_DSPP_AD_INPUT, 0, U16_MAX, 0); SDE_CP_CRTC_DSPP_AD_INPUT, 0, U16_MAX, 0); Loading drivers/gpu/drm/msm/sde/sde_crtc.c +4 −0 Original line number Original line Diff line number Diff line Loading @@ -1030,6 +1030,10 @@ static void _sde_crtc_program_lm_output_roi(struct drm_crtc *crtc) if (sde_kms_rect_is_null(lm_roi)) if (sde_kms_rect_is_null(lm_roi)) continue; continue; hw_lm->cfg.out_width = lm_roi->w; hw_lm->cfg.out_height = lm_roi->h; hw_lm->cfg.right_mixer = lm_horiz_position; cfg.out_width = lm_roi->w; cfg.out_width = lm_roi->w; cfg.out_height = lm_roi->h; cfg.out_height = lm_roi->h; cfg.right_mixer = lm_horiz_position++; cfg.right_mixer = lm_horiz_position++; Loading drivers/gpu/drm/msm/sde/sde_hw_ad4.c +6 −4 Original line number Original line Diff line number Diff line Loading @@ -17,8 +17,8 @@ #include "sde_ad4.h" #include "sde_ad4.h" #define IDLE_2_RUN(x) ((x) == (ad4_init | ad4_cfg | ad4_mode | ad4_input)) #define IDLE_2_RUN(x) ((x) == (ad4_init | ad4_cfg | ad4_mode | ad4_input)) #define MERGE_WIDTH_RIGHT 4 #define MERGE_WIDTH_RIGHT 6 #define MERGE_WIDTH_LEFT 3 #define MERGE_WIDTH_LEFT 5 enum ad4_ops_bitmask { enum ad4_ops_bitmask { ad4_init = BIT(AD_INIT), ad4_init = BIT(AD_INIT), Loading Loading @@ -179,7 +179,7 @@ static int ad4_params_check(struct sde_hw_dspp *dspp, cfg->hw_cfg->displayh, cfg->hw_cfg->displayv); cfg->hw_cfg->displayh, cfg->hw_cfg->displayv); return -EINVAL; return -EINVAL; } else if (hw_lm->cfg.out_height != cfg->hw_cfg->displayv && } else if (hw_lm->cfg.out_height != cfg->hw_cfg->displayv && hw_lm->cfg.out_width != (cfg->hw_cfg->displayh >> 2)) { hw_lm->cfg.out_width != (cfg->hw_cfg->displayh >> 1)) { DRM_ERROR("dual_lm lmh %d lmw %d displayh %d displayw %d\n", DRM_ERROR("dual_lm lmh %d lmw %d displayh %d displayw %d\n", hw_lm->cfg.out_height, hw_lm->cfg.out_width, hw_lm->cfg.out_height, hw_lm->cfg.out_width, cfg->hw_cfg->displayh, cfg->hw_cfg->displayv); cfg->hw_cfg->displayh, cfg->hw_cfg->displayv); Loading Loading @@ -250,6 +250,7 @@ static int ad4_init_setup(struct sde_hw_dspp *dspp, struct sde_ad_hw_cfg *cfg) MERGE_WIDTH_LEFT; MERGE_WIDTH_LEFT; proc_start = 0; proc_start = 0; proc_end = (cfg->hw_cfg->displayh >> 1) - 1; proc_end = (cfg->hw_cfg->displayh >> 1) - 1; tile_ctl |= 0x10; } } } } Loading Loading @@ -769,7 +770,8 @@ static int ad4_mode_setup_common(struct sde_hw_dspp *dspp, (cfg->hw_cfg->payload)); (cfg->hw_cfg->payload)); info[dspp->idx].completed_ops_mask |= ad4_mode; info[dspp->idx].completed_ops_mask |= ad4_mode; if (IDLE_2_RUN(info[dspp->idx].completed_ops_mask)) if (IDLE_2_RUN(info[dspp->idx].completed_ops_mask) || info[dspp->idx].cached_mode == AD4_OFF) ad4_mode_setup(dspp, info[dspp->idx].cached_mode); ad4_mode_setup(dspp, info[dspp->idx].cached_mode); return 0; return 0; Loading Loading
drivers/gpu/drm/msm/sde/sde_color_processing.c +1 −1 Original line number Original line Diff line number Diff line Loading @@ -1164,7 +1164,7 @@ static void dspp_ad_install_property(struct drm_crtc *crtc) sde_cp_create_local_blob(crtc, SDE_CP_CRTC_DSPP_AD_CFG, sde_cp_create_local_blob(crtc, SDE_CP_CRTC_DSPP_AD_CFG, sizeof(struct drm_msm_ad4_cfg)); sizeof(struct drm_msm_ad4_cfg)); sde_cp_crtc_install_range_property(crtc, sde_cp_crtc_install_range_property(crtc, "SDE_DSPP_AD_V4_ASSERTIVNESS", "SDE_DSPP_AD_V4_ASSERTIVENESS", SDE_CP_CRTC_DSPP_AD_ASSERTIVENESS, 0, (BIT(8) - 1), 0); SDE_CP_CRTC_DSPP_AD_ASSERTIVENESS, 0, (BIT(8) - 1), 0); sde_cp_crtc_install_range_property(crtc, "SDE_DSPP_AD_V4_INPUT", sde_cp_crtc_install_range_property(crtc, "SDE_DSPP_AD_V4_INPUT", SDE_CP_CRTC_DSPP_AD_INPUT, 0, U16_MAX, 0); SDE_CP_CRTC_DSPP_AD_INPUT, 0, U16_MAX, 0); Loading
drivers/gpu/drm/msm/sde/sde_crtc.c +4 −0 Original line number Original line Diff line number Diff line Loading @@ -1030,6 +1030,10 @@ static void _sde_crtc_program_lm_output_roi(struct drm_crtc *crtc) if (sde_kms_rect_is_null(lm_roi)) if (sde_kms_rect_is_null(lm_roi)) continue; continue; hw_lm->cfg.out_width = lm_roi->w; hw_lm->cfg.out_height = lm_roi->h; hw_lm->cfg.right_mixer = lm_horiz_position; cfg.out_width = lm_roi->w; cfg.out_width = lm_roi->w; cfg.out_height = lm_roi->h; cfg.out_height = lm_roi->h; cfg.right_mixer = lm_horiz_position++; cfg.right_mixer = lm_horiz_position++; Loading
drivers/gpu/drm/msm/sde/sde_hw_ad4.c +6 −4 Original line number Original line Diff line number Diff line Loading @@ -17,8 +17,8 @@ #include "sde_ad4.h" #include "sde_ad4.h" #define IDLE_2_RUN(x) ((x) == (ad4_init | ad4_cfg | ad4_mode | ad4_input)) #define IDLE_2_RUN(x) ((x) == (ad4_init | ad4_cfg | ad4_mode | ad4_input)) #define MERGE_WIDTH_RIGHT 4 #define MERGE_WIDTH_RIGHT 6 #define MERGE_WIDTH_LEFT 3 #define MERGE_WIDTH_LEFT 5 enum ad4_ops_bitmask { enum ad4_ops_bitmask { ad4_init = BIT(AD_INIT), ad4_init = BIT(AD_INIT), Loading Loading @@ -179,7 +179,7 @@ static int ad4_params_check(struct sde_hw_dspp *dspp, cfg->hw_cfg->displayh, cfg->hw_cfg->displayv); cfg->hw_cfg->displayh, cfg->hw_cfg->displayv); return -EINVAL; return -EINVAL; } else if (hw_lm->cfg.out_height != cfg->hw_cfg->displayv && } else if (hw_lm->cfg.out_height != cfg->hw_cfg->displayv && hw_lm->cfg.out_width != (cfg->hw_cfg->displayh >> 2)) { hw_lm->cfg.out_width != (cfg->hw_cfg->displayh >> 1)) { DRM_ERROR("dual_lm lmh %d lmw %d displayh %d displayw %d\n", DRM_ERROR("dual_lm lmh %d lmw %d displayh %d displayw %d\n", hw_lm->cfg.out_height, hw_lm->cfg.out_width, hw_lm->cfg.out_height, hw_lm->cfg.out_width, cfg->hw_cfg->displayh, cfg->hw_cfg->displayv); cfg->hw_cfg->displayh, cfg->hw_cfg->displayv); Loading Loading @@ -250,6 +250,7 @@ static int ad4_init_setup(struct sde_hw_dspp *dspp, struct sde_ad_hw_cfg *cfg) MERGE_WIDTH_LEFT; MERGE_WIDTH_LEFT; proc_start = 0; proc_start = 0; proc_end = (cfg->hw_cfg->displayh >> 1) - 1; proc_end = (cfg->hw_cfg->displayh >> 1) - 1; tile_ctl |= 0x10; } } } } Loading Loading @@ -769,7 +770,8 @@ static int ad4_mode_setup_common(struct sde_hw_dspp *dspp, (cfg->hw_cfg->payload)); (cfg->hw_cfg->payload)); info[dspp->idx].completed_ops_mask |= ad4_mode; info[dspp->idx].completed_ops_mask |= ad4_mode; if (IDLE_2_RUN(info[dspp->idx].completed_ops_mask)) if (IDLE_2_RUN(info[dspp->idx].completed_ops_mask) || info[dspp->idx].cached_mode == AD4_OFF) ad4_mode_setup(dspp, info[dspp->idx].cached_mode); ad4_mode_setup(dspp, info[dspp->idx].cached_mode); return 0; return 0; Loading