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Commit d61fb48b authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux 

Pull drm fixes from Dave Airlie:
 "i915, nouveau and amdgpu/radeon fixes in this:

  nouveau:
     Two fixes, one for a regression with dithering and one for a bug
     hit by the userspace drivers.

  i915:
     A few fixes, mostly things heading for stable, two important
     skylake GT3/4 hangs.

  radeon/amdgpu:
     Some audio, suspend/resume and some runtime PM fixes, along with
     two patches to harden the userptr ABI a bit"

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: (24 commits)
  drm: Loongson-3 doesn't fully support wc memory
  drm/nouveau/gr/gf100: select a stream master to fixup tfb offset queries
  amdgpu/uvd: add uvd fw version for amdgpu
  drm/amdgpu: forbid mapping of userptr bo through radeon device file
  drm/radeon: forbid mapping of userptr bo through radeon device file
  drm/amdgpu: bump the afmt limit for CZ, ST, Polaris
  drm/amdgpu: use defines for CRTCs and AMFT blocks
  drm/dp/mst: Validate port in drm_dp_payload_send_msg()
  drm/nouveau/kms: fix setting of default values for dithering properties
  drm/radeon: print a message if ATPX dGPU power control is missing
  Revert "drm/radeon: disable runtime pm on PX laptops without dGPU power control"
  drm/amdgpu/acp: fix resume on CZ systems with AZ audio
  drm/radeon: add a quirk for a XFX R9 270X
  drm/radeon: print pci revision as well as pci ids on driver load
  drm/i915: Use fw_domains_put_with_fifo() on HSW
  drm/i915: Force ringbuffers to not be at offset 0
  drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write
  drm/i915/skl: Fix spurious gpu hang with gt3/gt4 revs
  drm/i915/skl: Fix rc6 based gpu/system hang
  drm/i915/userptr: Hold mmref whilst calling get-user-pages
  ...
parents d4b05288 18cdfe75

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+1 −0
Original line number Diff line number Diff line
@@ -1591,6 +1591,7 @@ struct amdgpu_uvd { 
	struct amdgpu_bo	*vcpu_bo;

	void			*cpu_addr;

	uint64_t		gpu_addr;

	unsigned		fw_version;

	void			*saved_bo;

	atomic_t		handles[AMDGPU_MAX_UVD_HANDLES];

	struct drm_file		*filp[AMDGPU_MAX_UVD_HANDLES];

drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c

+4 −0
Original line number Diff line number Diff line
@@ -425,6 +425,10 @@ static int acp_resume(void *handle) 
	struct acp_pm_domain *apd;

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	/* return early if no ACP */

	if (!adev->acp.acp_genpd)

		return 0;



	/* SMU block will power on ACP irrespective of ACP runtime status.

	 * Power off explicitly based on genpd ACP runtime status so that ACP

	 * hw and ACP-genpd status are in sync.

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

+1 −1
Original line number Diff line number Diff line
@@ -303,7 +303,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file 
			fw_info.feature = adev->vce.fb_version;

			break;

		case AMDGPU_INFO_FW_UVD:

			fw_info.ver = 0;

			fw_info.ver = adev->uvd.fw_version;

			fw_info.feature = 0;

			break;

		case AMDGPU_INFO_FW_GMC:

drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h

+3 −3
Original line number Diff line number Diff line
@@ -53,7 +53,7 @@ struct amdgpu_hpd; 


#define AMDGPU_MAX_HPD_PINS 6

#define AMDGPU_MAX_CRTCS 6

#define AMDGPU_MAX_AFMT_BLOCKS 7

#define AMDGPU_MAX_AFMT_BLOCKS 9



enum amdgpu_rmx_type {

	RMX_OFF,
@@ -309,8 +309,8 @@ struct amdgpu_mode_info { 
	struct atom_context *atom_context;

	struct card_info *atom_card_info;

	bool mode_config_initialized;

	struct amdgpu_crtc *crtcs[6];

	struct amdgpu_afmt *afmt[7];

	struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS];

	struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS];

	/* DVI-I properties */

	struct drm_property *coherent_mode_property;

	/* DAC enable load detect */

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

+2 −0
Original line number Diff line number Diff line
@@ -223,6 +223,8 @@ static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp) 
{

	struct amdgpu_bo *rbo = container_of(bo, struct amdgpu_bo, tbo);



	if (amdgpu_ttm_tt_get_usermm(bo->ttm))

		return -EPERM;

	return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp);

}