Merge "ARM: dts: msm: Enabled audio path on OpenQ 624 SoM" (d5db5c63) · Commits · e / devices / android_kernel_fairphone_FP3

arch/arm64/boot/dts/qcom/apq8053-lite-dragon.dtsi

+50 −0

Original line number	Diff line number	Diff line
		@@ -87,6 +87,21 @@
		compatible = "qca,qca6174";
		qca,bt-reset-gpio = <&tlmm 76 0>; /* BT_EN */
		};

		cdc_dmic_gpios: cdc_dmic_pinctrl {
		compatible = "qcom,msm-cdc-pinctrl";
		pinctrl-names = "aud_active", "aud_sleep";
		pinctrl-0 = <&cdc_dmic0_clk_act &cdc_dmic0_data_act>;
		pinctrl-1 = <&cdc_dmic0_clk_sus &cdc_dmic0_data_sus>;
		};

		cdc_quat_mi2s_gpios: msm_cdc_pinctrl_quat {
		compatible = "qcom,msm-cdc-pinctrl";
		pinctrl-names = "aud_active", "aud_sleep";
		pinctrl-0 = <&sec_tlmm_lines_act>;
		pinctrl-1 = <&sec_tlmm_lines_sus>;
		};

		};

		&firmware {
		@@ -125,10 +140,45 @@
		};
		};

		&int_codec {
		status = "ok";
		qcom,model = "msm8953-openq624-snd-card";

		/delete-property/ qcom,cdc-us-euro-gpios;
		qcom,msm-hs-micbias-type = "internal";

		qcom,audio-routing =
		"RX_BIAS", "MCLK",
		"SPK_RX_BIAS", "MCLK",
		"INT_LDO_H", "MCLK",
		"MIC BIAS Internal1", "Handset Mic",
		"MIC BIAS Internal2", "Headset Mic",
		"MIC BIAS Internal1", "Secondary Mic",
		"AMIC1", "MIC BIAS Internal1",
		"AMIC2", "MIC BIAS Internal2",
		"AMIC3", "MIC BIAS Internal1",
		"DMIC1", "MIC BIAS Internal1",
		"MIC BIAS Internal1", "Digital Mic1",
		"DMIC2", "MIC BIAS Internal1",
		"MIC BIAS Internal1", "Digital Mic2";

		qcom,quat-mi2s-gpios = <&cdc_quat_mi2s_gpios>;
		qcom,cdc-dmic-gpios = <&cdc_dmic_gpios>;

		/delete-property/ asoc-wsa-codec-names;
		/delete-property/ asoc-wsa-codec-prefixes;
		/delete-property/ msm-vdd-wsa-switch-supply;
		/delete-property/ qcom,msm-vdd-wsa-switch-voltage;
		/delete-property/ qcom,msm-vdd-wsa-switch-current;
		};
		&spi_3 {
		status = "disabled";
		};

		&i2c_1 {
		status = "okay";
		};

		&i2c_2 {
		status = "okay";
		};

arch/arm64/boot/dts/qcom/msm8953-pinctrl.dtsi

+107 −0

Original line number	Diff line number	Diff line
		@@ -466,6 +466,87 @@
		};
		};

		cdc_dmic0_clk_act: cdc_dmic0_clk_act_default {
		mux {
		pins = "gpio89";
		function = "dmic0_clk";
		};

		config {
		pins = "gpio89";
		drive-strength = <8>;
		};
		};

		cdc_dmic0_clk_sus: cdc_dmic0_clk_sus_sleep {
		mux {
		pins = "gpio89";
		function = "gpio";
		};

		config {
		pins = "gpio89";
		drive-strength = <2>;
		bias-disable;
		};
		};

		cdc_dmic0_data_act: cdc_dmic0_data_act_default {
		mux {
		pins = "gpio90";
		function = "dmic0_data";
		};

		config {
		pins = "gpio90";
		drive-strength = <8>;
		};
		};

		cdc_dmic0_data_sus: cdc_dmic0_data_sus_sleep {
		mux {
		pins = "gpio90";
		function = "gpio";
		};

		config {
		pins = "gpio90";
		drive-strength = <2>;
		bias-disable;
		};
		};

		sec-tlmm-lines {
		sec_tlmm_lines_act: sec_tlmm_lines_act {
		mux {
		pins = "gpio135", "gpio136",
		"gpio137", "gpio138";
		function = "sec_mi2s";
		};

		config {
		pins = "gpio135", "gpio136",
		"gpio137", "gpio138";
		drive-strength = <8>;
		};
		};

		sec_tlmm_lines_sus: sec_tlmm_lines_sus {
		mux {
		pins = "gpio135", "gpio136",
		"gpio137", "gpio138";
		function = "sec_mi2s";
		};

		config {
		pins = "gpio135", "gpio136",
		"gpio137", "gpio138";
		drive-strength = <2>;
		bias-pull-down;
		};
		};
		};

		hsuart_active: default {
		mux {
		pins = "gpio12", "gpio13", "gpio14", "gpio15";
		@@ -656,6 +737,32 @@
		};
		};

		i2c_1 {
		i2c_1_active: i2c_1_active {
		mux {
		pins = "gpio2", "gpio3";
		function = "blsp_i2c1";
		};
		config {
		pins = "gpio2", "gpio3";
		drive-strength = <2>;
		bias-pull-up;
		};
		};

		i2c_1_sleep: i2c_1_sleep {
		mux {
		pins = "gpio2", "gpio3";
		function = "blsp_i2c1";
		};
		config {
		pins = "gpio2", "gpio3";
		drive-strength = <2>;
		bias-disable;
		};
		};
		};

		i2c_2 {
		i2c_2_active: i2c_2_active {
		/* active state */

arch/arm64/boot/dts/qcom/msm8953.dtsi

+25 −0

Original line number	Diff line number	Diff line
		@@ -161,6 +161,7 @@
		smd36 = &smdtty_loopback;
		sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
		sdhc2 = &sdhc_2; /* SDC2 for SD card */
		i2c1 = &i2c_1;
		i2c2 = &i2c_2;
		i2c3 = &i2c_3;
		i2c5 = &i2c_5;
		@@ -644,6 +645,30 @@
		qcom,master-id = <86>;
		status = "disabled";
		};
		i2c_1: i2c@78b5000 { /* BLSP1 QUP1 */
		compatible = "qcom,i2c-msm-v2";
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "qup_phys_addr";
		reg = <0x78b5000 0x600>;
		interrupt-names = "qup_irq";
		interrupts = <0 95 0>;
		qcom,master-id = <86>;
		qcom,clk-freq-out = <100000>;
		qcom,clk-freq-in = <19200000>;
		clock-names = "iface_clk", "core_clk";
		clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
		<&clock_gcc clk_gcc_blsp1_qup1_i2c_apps_clk>;
		pinctrl-names = "i2c_active", "i2c_sleep";
		pinctrl-0 = <&i2c_1_active>;
		pinctrl-1 = <&i2c_1_sleep>;
		qcom,noise-rjct-scl = <0>;
		qcom,noise-rjct-sda = <0>;
		dmas = <&dma_blsp1 4 64 0x20000020 0x20>,
		<&dma_blsp1 5 32 0x20000020 0x20>;
		dma-names = "tx", "rx";
		status = "disabled";
		};

		i2c_2: i2c@78b6000 { /* BLSP1 QUP2 */
		compatible = "qcom,i2c-msm-v2";