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Commit d5bb2da0 authored by Mitchel Humpherys's avatar Mitchel Humpherys Committed by Patrick Daly
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iommu/io-pgtable-arm: Use non-cacheable page table memory 



Requests from the walker to page table memory are currently inner- and
outer-cacheable.  This configuration hasn't been fully validated for
functionality or characterized for performance.  Configure these
requests as non-cacheable.

Change-Id: I7efb0a697faff68a67ee0afdb933b6dd6926f30a
Signed-off-by: default avatarMitchel Humpherys <mitchelh@codeaurora.org>
Signed-off-by: default avatarPatrick Daly <pdaly@codeaurora.org>
parent 73230ce4

drivers/iommu/io-pgtable-arm.c

+2 −2
Original line number Diff line number Diff line
@@ -930,8 +930,8 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie) 


	/* TCR */

	reg = (ARM_LPAE_TCR_SH_IS << ARM_LPAE_TCR_SH0_SHIFT) |

	      (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_IRGN0_SHIFT) |

	      (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_ORGN0_SHIFT);

	      (ARM_LPAE_TCR_RGN_NC << ARM_LPAE_TCR_IRGN0_SHIFT) |

	      (ARM_LPAE_TCR_RGN_NC << ARM_LPAE_TCR_ORGN0_SHIFT);



	switch (ARM_LPAE_GRANULE(data)) {

	case SZ_4K: