Loading Documentation/devicetree/bindings/regulator/cprh-kbss-regulator.txt +34 −0 Original line number Diff line number Diff line Loading @@ -185,6 +185,40 @@ KBSS specific properties: Definition: The initial temp band considering 0-based index at which the baseline target quotients are derived and fused. - qcom,cpr-acd-adj-down-step-limit Usage: required if qcom,cpr-acd-avg-enable is specified. Value type: <u32> Definition: The maximum number of PMIC steps to go down within a given corner due to all ACD adjustment recommendations. Valid values are 0 through 31. - qcom,cpr-acd-adj-up-step-limit Usage: required if qcom,cpr-acd-avg-enable is specified. Value type: <u32> Definition: The maximum number of PMIC steps to go up within a given corner due to all ACD adjustment recommendations. Valid values are 0 through 7 - qcom,cpr-acd-adj-down-step-size Usage: required if qcom,cpr-acd-avg-enable is specified. Value type: <u32> Definition: Defines the step size in units of PMIC steps used for target quotient adjustment due to an ACD down recommendation. Valid values are 0 through 3. - qcom,cpr-acd-adj-up-step-size Usage: required if qcom,cpr-acd-avg-enable is specified. Value type: <u32> Definition: Defines the step size in units of PMIC steps used for target quotient adjustment due to an ACD up recommendation. Valid values are 0 through 3. - qcom,cpr-acd-avg-enable Usage: optional Value type: <empty> Definition: Boolean flag which indicates that the CPRh controller should enable the ACD AVG feature. ================================================= Second Level Nodes - CPR Threads for a Controller ================================================= Loading drivers/regulator/cpr3-regulator.c +39 −0 Original line number Diff line number Diff line Loading @@ -280,6 +280,18 @@ ((vband) == 0 ? CPR4_REG_MARGIN_TEMP_CORE(core) \ : 0x3AB0 + 0x40 * ((vband) - 1) + 0x4 * (core)) #define CPRH_REG_MISC_REG2 0x3AAC #define CPRH_MISC_REG2_ACD_ADJ_STEP_UP_LIMIT_MASK GENMASK(31, 29) #define CPRH_MISC_REG2_ACD_ADJ_STEP_UP_LIMIT_SHIFT 29 #define CPRH_MISC_REG2_ACD_ADJ_STEP_DOWN_LIMIT_MASK GENMASK(28, 24) #define CPRH_MISC_REG2_ACD_ADJ_STEP_DOWN_LIMIT_SHIFT 24 #define CPRH_MISC_REG2_ACD_ADJ_STEP_SIZE_UP_MASK GENMASK(23, 22) #define CPRH_MISC_REG2_ACD_ADJ_STEP_SIZE_UP_SHIFT 22 #define CPRH_MISC_REG2_ACD_ADJ_STEP_SIZE_DOWN_MASK GENMASK(21, 20) #define CPRH_MISC_REG2_ACD_ADJ_STEP_SIZE_DOWN_SHIFT 20 #define CPRH_MISC_REG2_ACD_AVG_EN_MASK BIT(12) #define CPRH_MISC_REG2_ACD_AVG_ENABLE BIT(12) /* SAW module registers */ #define SAW_REG_AVS_CTL 0x904 #define SAW_REG_AVS_LIMIT 0x908 Loading Loading @@ -1398,6 +1410,33 @@ static int cpr3_regulator_init_cprh(struct cpr3_controller *ctrl) temp << CPRH_CTL_MODE_SWITCH_DELAY_SHIFT); } /* * Configure CPRh ACD AVG registers on controllers * that support this feature. */ if (ctrl->cpr_hw_version >= CPRH_CPR_VERSION_4P5 && ctrl->acd_avg_enabled) { cpr3_masked_write(ctrl, CPRH_REG_MISC_REG2, CPRH_MISC_REG2_ACD_ADJ_STEP_UP_LIMIT_MASK, ctrl->acd_adj_up_step_limit << CPRH_MISC_REG2_ACD_ADJ_STEP_UP_LIMIT_SHIFT); cpr3_masked_write(ctrl, CPRH_REG_MISC_REG2, CPRH_MISC_REG2_ACD_ADJ_STEP_DOWN_LIMIT_MASK, ctrl->acd_adj_down_step_limit << CPRH_MISC_REG2_ACD_ADJ_STEP_DOWN_LIMIT_SHIFT); cpr3_masked_write(ctrl, CPRH_REG_MISC_REG2, CPRH_MISC_REG2_ACD_ADJ_STEP_SIZE_UP_MASK, ctrl->acd_adj_up_step_size << CPRH_MISC_REG2_ACD_ADJ_STEP_SIZE_UP_SHIFT); cpr3_masked_write(ctrl, CPRH_REG_MISC_REG2, CPRH_MISC_REG2_ACD_ADJ_STEP_SIZE_DOWN_MASK, ctrl->acd_adj_down_step_size << CPRH_MISC_REG2_ACD_ADJ_STEP_SIZE_DOWN_SHIFT); cpr3_masked_write(ctrl, CPRH_REG_MISC_REG2, CPRH_MISC_REG2_ACD_AVG_EN_MASK, CPRH_MISC_REG2_ACD_AVG_ENABLE); } /* * Program base voltage and voltage multiplier values which * are used for floor and initial voltage calculations by the Loading drivers/regulator/cpr3-regulator.h +19 −0 Original line number Diff line number Diff line Loading @@ -649,6 +649,20 @@ struct cpr3_panic_regs_info { * defines the maximum number of VDD supply regulator steps * that the voltage may be increased as the result of a * single CPR measurement. * @acd_adj_down_step_limit: Limits the number of PMIC steps to go down within * a given corner due to all ACD adjustments on some CPRh * controllers. * @acd_adj_up_step_limit: Limits the number of PMIC steps to go up within a * given corner due to all ACD adjustments on some CPRh * controllers. * @acd_adj_down_step_size: ACD step size in units of PMIC steps used for * target quotient adjustment due to an ACD down * recommendation. * @acd_adj_up_step_size: ACD step size in units of PMIC steps used for * target quotient adjustment due to an ACD up * recommendation. * @acd_avg_enabled: Boolean defining the enable state of the ACD AVG * feature. * @count_mode: CPR controller count mode * @count_repeat: Number of times to perform consecutive sensor * measurements when using all-at-once count modes. Loading Loading @@ -804,6 +818,11 @@ struct cpr3_controller { int step_volt; u32 down_error_step_limit; u32 up_error_step_limit; u32 acd_adj_down_step_limit; u32 acd_adj_up_step_limit; u32 acd_adj_down_step_size; u32 acd_adj_up_step_size; bool acd_avg_enabled; enum cpr3_count_mode count_mode; u32 count_repeat; u32 proc_clock_throttle; Loading drivers/regulator/cprh-kbss-regulator.c +40 −0 Original line number Diff line number Diff line Loading @@ -2221,6 +2221,46 @@ static int cprh_kbss_init_controller(struct cpr3_controller *ctrl) return rc; } ctrl->acd_avg_enabled = of_property_read_bool(ctrl->dev->of_node, "qcom,cpr-acd-avg-enable"); if (ctrl->acd_avg_enabled) { rc = of_property_read_u32(ctrl->dev->of_node, "qcom,cpr-acd-adj-down-step-limit", &ctrl->acd_adj_down_step_limit); if (rc) { cpr3_err(ctrl, "error reading qcom,cpr-acd-adj-down-step-limit, rc=%d\n", rc); return rc; } rc = of_property_read_u32(ctrl->dev->of_node, "qcom,cpr-acd-adj-up-step-limit", &ctrl->acd_adj_up_step_limit); if (rc) { cpr3_err(ctrl, "error reading qcom,cpr-acd-adj-up-step-limit, rc=%d\n", rc); return rc; } rc = of_property_read_u32(ctrl->dev->of_node, "qcom,cpr-acd-adj-down-step-size", &ctrl->acd_adj_down_step_size); if (rc) { cpr3_err(ctrl, "error reading qcom,cpr-acd-down-step-size, rc=%d\n", rc); return rc; } rc = of_property_read_u32(ctrl->dev->of_node, "qcom,cpr-acd-adj-up-step-size", &ctrl->acd_adj_up_step_size); if (rc) { cpr3_err(ctrl, "error reading qcom,cpr-acd-up-step-size, rc=%d\n", rc); return rc; } } rc = of_property_read_u32(ctrl->dev->of_node, "qcom,voltage-base", &ctrl->base_volt); Loading Loading
Documentation/devicetree/bindings/regulator/cprh-kbss-regulator.txt +34 −0 Original line number Diff line number Diff line Loading @@ -185,6 +185,40 @@ KBSS specific properties: Definition: The initial temp band considering 0-based index at which the baseline target quotients are derived and fused. - qcom,cpr-acd-adj-down-step-limit Usage: required if qcom,cpr-acd-avg-enable is specified. Value type: <u32> Definition: The maximum number of PMIC steps to go down within a given corner due to all ACD adjustment recommendations. Valid values are 0 through 31. - qcom,cpr-acd-adj-up-step-limit Usage: required if qcom,cpr-acd-avg-enable is specified. Value type: <u32> Definition: The maximum number of PMIC steps to go up within a given corner due to all ACD adjustment recommendations. Valid values are 0 through 7 - qcom,cpr-acd-adj-down-step-size Usage: required if qcom,cpr-acd-avg-enable is specified. Value type: <u32> Definition: Defines the step size in units of PMIC steps used for target quotient adjustment due to an ACD down recommendation. Valid values are 0 through 3. - qcom,cpr-acd-adj-up-step-size Usage: required if qcom,cpr-acd-avg-enable is specified. Value type: <u32> Definition: Defines the step size in units of PMIC steps used for target quotient adjustment due to an ACD up recommendation. Valid values are 0 through 3. - qcom,cpr-acd-avg-enable Usage: optional Value type: <empty> Definition: Boolean flag which indicates that the CPRh controller should enable the ACD AVG feature. ================================================= Second Level Nodes - CPR Threads for a Controller ================================================= Loading
drivers/regulator/cpr3-regulator.c +39 −0 Original line number Diff line number Diff line Loading @@ -280,6 +280,18 @@ ((vband) == 0 ? CPR4_REG_MARGIN_TEMP_CORE(core) \ : 0x3AB0 + 0x40 * ((vband) - 1) + 0x4 * (core)) #define CPRH_REG_MISC_REG2 0x3AAC #define CPRH_MISC_REG2_ACD_ADJ_STEP_UP_LIMIT_MASK GENMASK(31, 29) #define CPRH_MISC_REG2_ACD_ADJ_STEP_UP_LIMIT_SHIFT 29 #define CPRH_MISC_REG2_ACD_ADJ_STEP_DOWN_LIMIT_MASK GENMASK(28, 24) #define CPRH_MISC_REG2_ACD_ADJ_STEP_DOWN_LIMIT_SHIFT 24 #define CPRH_MISC_REG2_ACD_ADJ_STEP_SIZE_UP_MASK GENMASK(23, 22) #define CPRH_MISC_REG2_ACD_ADJ_STEP_SIZE_UP_SHIFT 22 #define CPRH_MISC_REG2_ACD_ADJ_STEP_SIZE_DOWN_MASK GENMASK(21, 20) #define CPRH_MISC_REG2_ACD_ADJ_STEP_SIZE_DOWN_SHIFT 20 #define CPRH_MISC_REG2_ACD_AVG_EN_MASK BIT(12) #define CPRH_MISC_REG2_ACD_AVG_ENABLE BIT(12) /* SAW module registers */ #define SAW_REG_AVS_CTL 0x904 #define SAW_REG_AVS_LIMIT 0x908 Loading Loading @@ -1398,6 +1410,33 @@ static int cpr3_regulator_init_cprh(struct cpr3_controller *ctrl) temp << CPRH_CTL_MODE_SWITCH_DELAY_SHIFT); } /* * Configure CPRh ACD AVG registers on controllers * that support this feature. */ if (ctrl->cpr_hw_version >= CPRH_CPR_VERSION_4P5 && ctrl->acd_avg_enabled) { cpr3_masked_write(ctrl, CPRH_REG_MISC_REG2, CPRH_MISC_REG2_ACD_ADJ_STEP_UP_LIMIT_MASK, ctrl->acd_adj_up_step_limit << CPRH_MISC_REG2_ACD_ADJ_STEP_UP_LIMIT_SHIFT); cpr3_masked_write(ctrl, CPRH_REG_MISC_REG2, CPRH_MISC_REG2_ACD_ADJ_STEP_DOWN_LIMIT_MASK, ctrl->acd_adj_down_step_limit << CPRH_MISC_REG2_ACD_ADJ_STEP_DOWN_LIMIT_SHIFT); cpr3_masked_write(ctrl, CPRH_REG_MISC_REG2, CPRH_MISC_REG2_ACD_ADJ_STEP_SIZE_UP_MASK, ctrl->acd_adj_up_step_size << CPRH_MISC_REG2_ACD_ADJ_STEP_SIZE_UP_SHIFT); cpr3_masked_write(ctrl, CPRH_REG_MISC_REG2, CPRH_MISC_REG2_ACD_ADJ_STEP_SIZE_DOWN_MASK, ctrl->acd_adj_down_step_size << CPRH_MISC_REG2_ACD_ADJ_STEP_SIZE_DOWN_SHIFT); cpr3_masked_write(ctrl, CPRH_REG_MISC_REG2, CPRH_MISC_REG2_ACD_AVG_EN_MASK, CPRH_MISC_REG2_ACD_AVG_ENABLE); } /* * Program base voltage and voltage multiplier values which * are used for floor and initial voltage calculations by the Loading
drivers/regulator/cpr3-regulator.h +19 −0 Original line number Diff line number Diff line Loading @@ -649,6 +649,20 @@ struct cpr3_panic_regs_info { * defines the maximum number of VDD supply regulator steps * that the voltage may be increased as the result of a * single CPR measurement. * @acd_adj_down_step_limit: Limits the number of PMIC steps to go down within * a given corner due to all ACD adjustments on some CPRh * controllers. * @acd_adj_up_step_limit: Limits the number of PMIC steps to go up within a * given corner due to all ACD adjustments on some CPRh * controllers. * @acd_adj_down_step_size: ACD step size in units of PMIC steps used for * target quotient adjustment due to an ACD down * recommendation. * @acd_adj_up_step_size: ACD step size in units of PMIC steps used for * target quotient adjustment due to an ACD up * recommendation. * @acd_avg_enabled: Boolean defining the enable state of the ACD AVG * feature. * @count_mode: CPR controller count mode * @count_repeat: Number of times to perform consecutive sensor * measurements when using all-at-once count modes. Loading Loading @@ -804,6 +818,11 @@ struct cpr3_controller { int step_volt; u32 down_error_step_limit; u32 up_error_step_limit; u32 acd_adj_down_step_limit; u32 acd_adj_up_step_limit; u32 acd_adj_down_step_size; u32 acd_adj_up_step_size; bool acd_avg_enabled; enum cpr3_count_mode count_mode; u32 count_repeat; u32 proc_clock_throttle; Loading
drivers/regulator/cprh-kbss-regulator.c +40 −0 Original line number Diff line number Diff line Loading @@ -2221,6 +2221,46 @@ static int cprh_kbss_init_controller(struct cpr3_controller *ctrl) return rc; } ctrl->acd_avg_enabled = of_property_read_bool(ctrl->dev->of_node, "qcom,cpr-acd-avg-enable"); if (ctrl->acd_avg_enabled) { rc = of_property_read_u32(ctrl->dev->of_node, "qcom,cpr-acd-adj-down-step-limit", &ctrl->acd_adj_down_step_limit); if (rc) { cpr3_err(ctrl, "error reading qcom,cpr-acd-adj-down-step-limit, rc=%d\n", rc); return rc; } rc = of_property_read_u32(ctrl->dev->of_node, "qcom,cpr-acd-adj-up-step-limit", &ctrl->acd_adj_up_step_limit); if (rc) { cpr3_err(ctrl, "error reading qcom,cpr-acd-adj-up-step-limit, rc=%d\n", rc); return rc; } rc = of_property_read_u32(ctrl->dev->of_node, "qcom,cpr-acd-adj-down-step-size", &ctrl->acd_adj_down_step_size); if (rc) { cpr3_err(ctrl, "error reading qcom,cpr-acd-down-step-size, rc=%d\n", rc); return rc; } rc = of_property_read_u32(ctrl->dev->of_node, "qcom,cpr-acd-adj-up-step-size", &ctrl->acd_adj_up_step_size); if (rc) { cpr3_err(ctrl, "error reading qcom,cpr-acd-up-step-size, rc=%d\n", rc); return rc; } } rc = of_property_read_u32(ctrl->dev->of_node, "qcom,voltage-base", &ctrl->base_volt); Loading
