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Commit d431440c authored by Tomas Elf's avatar Tomas Elf Committed by Mika Kuoppala
Browse files

drm/i915: Generalise common GPU engine reset request/unrequest code 



GPU engine reset handshaking is something that is applicable to both full GPU
reset and engine reset, which is something that is part of the upcoming TDR
per-engine hang recovery patches. Break out the common engine reset
request/unrequest code (originally written by Mika Kuoppala) for reuse later
in the TDR enablement patch series.

v2: correct indentation and drop unused returned value (Mika)
v3: We have forcewake during reset so use *_FW reg access (Mika)

Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: default avatarTomas Elf <tomas.elf@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: default avatarArun Siluvery <arun.siluvery@linux.intel.com>
[Mika: Fixed format warning]
Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1456929984-16323-1-git-send-email-mika.kuoppala@intel.com
parent 37f2248e

drivers/gpu/drm/i915/intel_uncore.c

+36 −20
Original line number Diff line number Diff line
@@ -1531,41 +1531,57 @@ static int gen6_do_reset(struct drm_device *dev) 
	return ret;

}



static int wait_for_register(struct drm_i915_private *dev_priv,

static int wait_for_register_fw(struct drm_i915_private *dev_priv,

				i915_reg_t reg,

				const u32 mask,

				const u32 value,

				const unsigned long timeout_ms)

{

	return wait_for((I915_READ(reg) & mask) == value, timeout_ms);

	return wait_for((I915_READ_FW(reg) & mask) == value, timeout_ms);

}



static int gen8_do_reset(struct drm_device *dev)

static int gen8_request_engine_reset(struct intel_engine_cs *engine)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_engine_cs *engine;

	int i;

	int ret;

	struct drm_i915_private *dev_priv = engine->dev->dev_private;



	for_each_ring(engine, dev_priv, i) {

		I915_WRITE(RING_RESET_CTL(engine->mmio_base),

	I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),

		      _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));



		if (wait_for_register(dev_priv,

	ret = wait_for_register_fw(dev_priv,

				   RING_RESET_CTL(engine->mmio_base),

				   RESET_CTL_READY_TO_RESET,

				   RESET_CTL_READY_TO_RESET,

				      700)) {

				   700);

	if (ret)

		DRM_ERROR("%s: reset request timeout\n", engine->name);

			goto not_ready;



	return ret;

}



static void gen8_unrequest_engine_reset(struct intel_engine_cs *engine)

{

	struct drm_i915_private *dev_priv = engine->dev->dev_private;



	I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),

		      _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));

}



static int gen8_do_reset(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_engine_cs *engine;

	int i;



	for_each_ring(engine, dev_priv, i)

		if (gen8_request_engine_reset(engine))

			goto not_ready;



	return gen6_do_reset(dev);



not_ready:

	for_each_ring(engine, dev_priv, i)

		I915_WRITE(RING_RESET_CTL(engine->mmio_base),

			   _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));

		gen8_unrequest_engine_reset(engine);



	return -EIO;

}