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Commit d3756c00 authored by Sushmita Susheelendra's avatar Sushmita Susheelendra Committed by Gerrit - the friendly Code Review server
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msm: kgsl: Add sysfs node to enable/disable GPUHTW LLC slice



The change will take effect upon the next GPU wake-up.

CRs-Fixed: 1081617
Change-Id: I5f4bb20abd4945297f6692f7705e26acfc1b26ec
Signed-off-by: default avatarSushmita Susheelendra <ssusheel@codeaurora.org>
parent 906564d4
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+1 −0
Original line number Diff line number Diff line
@@ -111,6 +111,7 @@ static struct adreno_device device_3d0 = {
	.active_list = LIST_HEAD_INIT(device_3d0.active_list),
	.active_list_lock = __SPIN_LOCK_UNLOCKED(device_3d0.active_list_lock),
	.gpu_llc_slice_enable = true,
	.gpuhtw_llc_slice_enable = true,
};

/* Ptr to array for the current set of fault detect registers */
+2 −0
Original line number Diff line number Diff line
@@ -399,6 +399,7 @@ struct adreno_gpu_core {
 * @gpu_llc_slice: GPU system cache slice descriptor
 * @gpu_llc_slice_enable: To enable the GPU system cache slice or not
 * @gpuhtw_llc_slice: GPU pagetables system cache slice descriptor
 * @gpuhtw_llc_slice_enable: To enable the GPUHTW system cache slice or not
 */
struct adreno_device {
	struct kgsl_device dev;    /* Must be first field in this struct */
@@ -461,6 +462,7 @@ struct adreno_device {
	void *gpu_llc_slice;
	bool gpu_llc_slice_enable;
	void *gpuhtw_llc_slice;
	bool gpuhtw_llc_slice_enable;
};

/**
+1 −1
Original line number Diff line number Diff line
@@ -54,7 +54,7 @@ static inline void adreno_llc_setup(struct kgsl_device *device)
				gpudev->llc_configure_gpu_scid(adreno_dev);
		}

	if (adreno_dev->gpuhtw_llc_slice)
	if (adreno_dev->gpuhtw_llc_slice && adreno_dev->gpuhtw_llc_slice_enable)
		if (!llcc_slice_activate(adreno_dev->gpuhtw_llc_slice)) {
			if (gpudev->llc_configure_gpuhtw_scid)
				gpudev->llc_configure_gpuhtw_scid(adreno_dev);
+15 −0
Original line number Diff line number Diff line
@@ -89,6 +89,19 @@ static unsigned int _gpu_llc_slice_enable_show(struct adreno_device *adreno_dev)
	return adreno_dev->gpu_llc_slice_enable;
}

static int _gpuhtw_llc_slice_enable_store(struct adreno_device *adreno_dev,
		unsigned int val)
{
	adreno_dev->gpuhtw_llc_slice_enable = val ? true : false;
	return 0;
}

static unsigned int
_gpuhtw_llc_slice_enable_show(struct adreno_device *adreno_dev)
{
	return adreno_dev->gpuhtw_llc_slice_enable;
}

static int _ft_long_ib_detect_store(struct adreno_device *adreno_dev,
		unsigned int val)
{
@@ -303,6 +316,7 @@ static ADRENO_SYSFS_U32(ft_pagefault_policy);
static ADRENO_SYSFS_BOOL(ft_long_ib_detect);
static ADRENO_SYSFS_BOOL(ft_hang_intr_status);
static ADRENO_SYSFS_BOOL(gpu_llc_slice_enable);
static ADRENO_SYSFS_BOOL(gpuhtw_llc_slice_enable);

static DEVICE_INT_ATTR(wake_nice, 0644, adreno_wake_nice);
static DEVICE_INT_ATTR(wake_timeout, 0644, adreno_wake_timeout);
@@ -328,6 +342,7 @@ static const struct device_attribute *_attr_list[] = {
	&adreno_attr_hwcg.attr,
	&adreno_attr_throttling.attr,
	&adreno_attr_gpu_llc_slice_enable.attr,
	&adreno_attr_gpuhtw_llc_slice_enable.attr,
	NULL,
};