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Commit d36f7453 authored by Tengfei Fan's avatar Tengfei Fan
Browse files

pinctrl: qcom: Clear status bit on irq_unmask 



The gpio interrupt status bit is getting set after the
irq is disabled and causing an immediate interrupt after
enablling the irq, so clear status bit on irq_unmask.

Change-Id: I89245b90b06b37671369e59c15fb24a991cc114a
Signed-off-by: default avatarTengfei Fan <tengfeif@codeaurora.org>
parent b6bf7795

drivers/pinctrl/qcom/pinctrl-msm.c

+7 −0
Original line number Diff line number Diff line
@@ -629,6 +629,7 @@ static void msm_gpio_irq_enable(struct irq_data *d) 
static void msm_gpio_irq_unmask(struct irq_data *d)

{

	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);

	uint32_t irqtype = irqd_get_trigger_type(d);

	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);

	const struct msm_pingroup *g;

	unsigned long flags;
@@ -638,6 +639,12 @@ static void msm_gpio_irq_unmask(struct irq_data *d) 


	spin_lock_irqsave(&pctrl->lock, flags);



	if (irqtype & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) {

		val = readl_relaxed(pctrl->regs + g->intr_status_reg);

		val &= ~BIT(g->intr_status_bit);

		writel_relaxed(val, pctrl->regs + g->intr_status_reg);

	}



	val = readl(pctrl->regs + g->intr_cfg_reg);

	val |= BIT(g->intr_enable_bit);

	writel(val, pctrl->regs + g->intr_cfg_reg);