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Commit d32dc9aa authored by Ludovic Desroches's avatar Ludovic Desroches Committed by Thomas Gleixner
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irqchip/atmel-aic5: Use per chip mask caches in mask/unmask() 



When masking/unmasking interrupts, mask_cache is updated and used later
for suspend/resume. Unfortunately, it always was the mask_cache
associated with the first irq chip which was updated. So when performing
resume, only irqs 0-31 could be enabled.

Fixes: b1479ebb ("irqchip: atmel-aic: Add atmel AIC/AIC5 drivers")
Signed-off-by: default avatarLudovic Desroches <ludovic.desroches@atmel.com>
Cc: <sasha.levin@oracle.com>
Cc: <linux-arm-kernel@lists.infradead.org>
Cc: <nicolas.ferre@atmel.com>
Cc: <alexandre.belloni@free-electrons.com>
Cc: <boris.brezillon@free-electrons.com>
Cc: <Wenyou.Yang@atmel.com>
Cc: <jason@lakedaemon.net>
Cc: <marc.zyngier@arm.com>
Cc: stable@vger.kernel.org #3.18
Link: http://lkml.kernel.org/r/1442843173-2390-1-git-send-email-ludovic.desroches@atmel.com


Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent 1f93e4a9

drivers/irqchip/irq-atmel-aic5.c

+16 −8
Original line number Diff line number Diff line
@@ -88,28 +88,36 @@ static void aic5_mask(struct irq_data *d) 
{

	struct irq_domain *domain = d->domain;

	struct irq_domain_chip_generic *dgc = domain->gc;

	struct irq_chip_generic *gc = dgc->gc[0];

	struct irq_chip_generic *bgc = dgc->gc[0];

	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);



	/* Disable interrupt on AIC5 */

	irq_gc_lock(gc);

	/*

	 * Disable interrupt on AIC5. We always take the lock of the

	 * first irq chip as all chips share the same registers.

	 */

	irq_gc_lock(bgc);

	irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR);

	irq_reg_writel(gc, 1, AT91_AIC5_IDCR);

	gc->mask_cache &= ~d->mask;

	irq_gc_unlock(gc);

	irq_gc_unlock(bgc);

}



static void aic5_unmask(struct irq_data *d)

{

	struct irq_domain *domain = d->domain;

	struct irq_domain_chip_generic *dgc = domain->gc;

	struct irq_chip_generic *gc = dgc->gc[0];

	struct irq_chip_generic *bgc = dgc->gc[0];

	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);



	/* Enable interrupt on AIC5 */

	irq_gc_lock(gc);

	/*

	 * Enable interrupt on AIC5. We always take the lock of the

	 * first irq chip as all chips share the same registers.

	 */

	irq_gc_lock(bgc);

	irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR);

	irq_reg_writel(gc, 1, AT91_AIC5_IECR);

	gc->mask_cache |= d->mask;

	irq_gc_unlock(gc);

	irq_gc_unlock(bgc);

}



static int aic5_retrigger(struct irq_data *d)