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Commit d2182b69 authored by Joe Perches's avatar Joe Perches Committed by John W. Linville
Browse files

ath: Convert ath_dbg(bar, ATH_DBG_<FOO>, to ath_dbg(bar, FOO 



Add ATH_DBG_ to macros to shorten the uses and
reduce the line count.

Coalesce ath_dbg formats.
Add missing spaces to coalesced formats.
Add missing newline terminations to ath_dbg formats.
Align ath_dbg arguments where appropriate.
Standardize ath_dbg formats without periods.

Signed-off-by: default avatarJoe Perches <joe@perches.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent a85e1d55

drivers/net/wireless/ath/ath.h

+5 −2
Original line number Diff line number Diff line
@@ -255,7 +255,7 @@ enum ATH_DEBUG { 


#define ath_dbg(common, dbg_mask, fmt, ...)				\

do {									\

	if ((common)->debug_mask & dbg_mask)				\

	if ((common)->debug_mask & ATH_DBG_##dbg_mask)			\

		_ath_printk(KERN_DEBUG, common, fmt, ##__VA_ARGS__);	\

} while (0)
@@ -265,10 +265,13 @@ do { \ 
#else



static inline  __attribute__ ((format (printf, 3, 4)))

void ath_dbg(struct ath_common *common, enum ATH_DEBUG dbg_mask,

void _ath_dbg(struct ath_common *common, enum ATH_DEBUG dbg_mask,

	     const char *fmt, ...)

{

}

#define ath_dbg(common, dbg_mask, fmt, ...)				\

	_ath_dbg(common, ATH_DBG_##dbg_mask, fmt, ##__VA_ARGS__)



#define ATH_DBG_WARN(foo, arg...) do {} while (0)

#define ATH_DBG_WARN_ON_ONCE(foo) ({				\

	int __ret_warn_once = !!(foo);				\

drivers/net/wireless/ath/ath9k/ani.c

+13 −16
Original line number Diff line number Diff line
@@ -136,8 +136,8 @@ static void ath9k_ani_restart(struct ath_hw *ah) 
		cck_base = AR_PHY_COUNTMAX - ah->config.cck_trig_high;

	}



	ath_dbg(common, ATH_DBG_ANI,

		"Writing ofdmbase=%u   cckbase=%u\n", ofdm_base, cck_base);

	ath_dbg(common, ANI, "Writing ofdmbase=%u   cckbase=%u\n",

		ofdm_base, cck_base);



	ENABLE_REGWRITE_BUFFER(ah);
@@ -268,8 +268,7 @@ static void ath9k_hw_set_ofdm_nil(struct ath_hw *ah, u8 immunityLevel) 


	aniState->noiseFloor = BEACON_RSSI(ah);



	ath_dbg(common, ATH_DBG_ANI,

		"**** ofdmlevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",

	ath_dbg(common, ANI, "**** ofdmlevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",

		aniState->ofdmNoiseImmunityLevel,

		immunityLevel, aniState->noiseFloor,

		aniState->rssiThrLow, aniState->rssiThrHigh);
@@ -336,8 +335,7 @@ static void ath9k_hw_set_cck_nil(struct ath_hw *ah, u_int8_t immunityLevel) 
	const struct ani_cck_level_entry *entry_cck;



	aniState->noiseFloor = BEACON_RSSI(ah);

	ath_dbg(common, ATH_DBG_ANI,

		"**** ccklevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",

	ath_dbg(common, ANI, "**** ccklevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",

		aniState->cckNoiseImmunityLevel, immunityLevel,

		aniState->noiseFloor, aniState->rssiThrLow,

		aniState->rssiThrHigh);
@@ -481,8 +479,7 @@ static void ath9k_ani_reset_old(struct ath_hw *ah, bool is_scanning) 


	if (ah->opmode != NL80211_IFTYPE_STATION

	    && ah->opmode != NL80211_IFTYPE_ADHOC) {

		ath_dbg(common, ATH_DBG_ANI,

			"Reset ANI state opmode %u\n", ah->opmode);

		ath_dbg(common, ANI, "Reset ANI state opmode %u\n", ah->opmode);

		ah->stats.ast_ani_reset++;



		if (ah->opmode == NL80211_IFTYPE_AP) {
@@ -582,7 +579,7 @@ void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning) 
		    ATH9K_ANI_OFDM_DEF_LEVEL ||

		    aniState->cckNoiseImmunityLevel !=

		    ATH9K_ANI_CCK_DEF_LEVEL) {

			ath_dbg(common, ATH_DBG_ANI,

			ath_dbg(common, ANI,

				"Restore defaults: opmode %u chan %d Mhz/0x%x is_scanning=%d ofdm:%d cck:%d\n",

				ah->opmode,

				chan->channel,
@@ -599,7 +596,7 @@ void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning) 
		/*

		 * restore historical levels for this channel

		 */

		ath_dbg(common, ATH_DBG_ANI,

		ath_dbg(common, ANI,

			"Restore history: opmode %u chan %d Mhz/0x%x is_scanning=%d ofdm:%d cck:%d\n",

			ah->opmode,

			chan->channel,
@@ -662,7 +659,7 @@ static bool ath9k_hw_ani_read_counters(struct ath_hw *ah) 


	if (!use_new_ani(ah) && (phyCnt1 < ofdm_base || phyCnt2 < cck_base)) {

		if (phyCnt1 < ofdm_base) {

			ath_dbg(common, ATH_DBG_ANI,

			ath_dbg(common, ANI,

				"phyCnt1 0x%x, resetting counter value to 0x%x\n",

				phyCnt1, ofdm_base);

			REG_WRITE(ah, AR_PHY_ERR_1, ofdm_base);
@@ -670,7 +667,7 @@ static bool ath9k_hw_ani_read_counters(struct ath_hw *ah) 
				  AR_PHY_ERR_OFDM_TIMING);

		}

		if (phyCnt2 < cck_base) {

			ath_dbg(common, ATH_DBG_ANI,

			ath_dbg(common, ANI,

				"phyCnt2 0x%x, resetting counter value to 0x%x\n",

				phyCnt2, cck_base);

			REG_WRITE(ah, AR_PHY_ERR_2, cck_base);
@@ -713,7 +710,7 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan) 
	cckPhyErrRate =  aniState->cckPhyErrCount * 1000 /

			 aniState->listenTime;



	ath_dbg(common, ATH_DBG_ANI,

	ath_dbg(common, ANI,

		"listenTime=%d OFDM:%d errs=%d/s CCK:%d errs=%d/s ofdm_turn=%d\n",

		aniState->listenTime,

		aniState->ofdmNoiseImmunityLevel,
@@ -748,7 +745,7 @@ void ath9k_enable_mib_counters(struct ath_hw *ah) 
{

	struct ath_common *common = ath9k_hw_common(ah);



	ath_dbg(common, ATH_DBG_ANI, "Enable MIB counters\n");

	ath_dbg(common, ANI, "Enable MIB counters\n");



	ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
@@ -770,7 +767,7 @@ void ath9k_hw_disable_mib_counters(struct ath_hw *ah) 
{

	struct ath_common *common = ath9k_hw_common(ah);



	ath_dbg(common, ATH_DBG_ANI, "Disable MIB counters\n");

	ath_dbg(common, ANI, "Disable MIB counters\n");



	REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC);

	ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
@@ -845,7 +842,7 @@ void ath9k_hw_ani_init(struct ath_hw *ah) 
	struct ath_common *common = ath9k_hw_common(ah);

	int i;



	ath_dbg(common, ATH_DBG_ANI, "Initialize ANI\n");

	ath_dbg(common, ANI, "Initialize ANI\n");



	if (use_new_ani(ah)) {

		ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_NEW;

drivers/net/wireless/ath/ath9k/ar5008_phy.c

+19 −23
Original line number Diff line number Diff line
@@ -158,7 +158,7 @@ static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq) 
	/* pre-reverse this field */

	tmp_reg = ath9k_hw_reverse_bits(new_bias, 3);



	ath_dbg(common, ATH_DBG_CONFIG, "Force rf_pwd_icsyndiv to %1d on %4d\n",

	ath_dbg(common, CONFIG, "Force rf_pwd_icsyndiv to %1d on %4d\n",

		new_bias, synth_freq);



	/* swizzle rf_pwd_icsyndiv */
@@ -1053,8 +1053,7 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah, 
		u32 level = param;



		if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {

			ath_dbg(common, ATH_DBG_ANI,

				"level out of range (%u > %zu)\n",

			ath_dbg(common, ANI, "level out of range (%u > %zu)\n",

				level, ARRAY_SIZE(ah->totalSizeDesired));

			return false;

		}
@@ -1157,8 +1156,7 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah, 
		u32 level = param;



		if (level >= ARRAY_SIZE(firstep)) {

			ath_dbg(common, ATH_DBG_ANI,

				"level out of range (%u > %zu)\n",

			ath_dbg(common, ANI, "level out of range (%u > %zu)\n",

				level, ARRAY_SIZE(firstep));

			return false;

		}
@@ -1177,8 +1175,7 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah, 
		u32 level = param;



		if (level >= ARRAY_SIZE(cycpwrThr1)) {

			ath_dbg(common, ATH_DBG_ANI,

				"level out of range (%u > %zu)\n",

			ath_dbg(common, ANI, "level out of range (%u > %zu)\n",

				level, ARRAY_SIZE(cycpwrThr1));

			return false;

		}
@@ -1195,23 +1192,22 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah, 
	case ATH9K_ANI_PRESENT:

		break;

	default:

		ath_dbg(common, ATH_DBG_ANI, "invalid cmd %u\n", cmd);

		ath_dbg(common, ANI, "invalid cmd %u\n", cmd);

		return false;

	}



	ath_dbg(common, ATH_DBG_ANI, "ANI parameters:\n");

	ath_dbg(common, ATH_DBG_ANI,

	ath_dbg(common, ANI, "ANI parameters:\n");

	ath_dbg(common, ANI,

		"noiseImmunityLevel=%d, spurImmunityLevel=%d, ofdmWeakSigDetectOff=%d\n",

		aniState->noiseImmunityLevel,

		aniState->spurImmunityLevel,

		!aniState->ofdmWeakSigDetectOff);

	ath_dbg(common, ATH_DBG_ANI,

	ath_dbg(common, ANI,

		"cckWeakSigThreshold=%d, firstepLevel=%d, listenTime=%d\n",

		aniState->cckWeakSigThreshold,

		aniState->firstepLevel,

		aniState->listenTime);

	ath_dbg(common, ATH_DBG_ANI,

		"ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",

	ath_dbg(common, ANI, "ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",

		aniState->ofdmPhyErrCount,

		aniState->cckPhyErrCount);
@@ -1295,7 +1291,7 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah, 
				    AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);



		if (!on != aniState->ofdmWeakSigDetectOff) {

			ath_dbg(common, ATH_DBG_ANI,

			ath_dbg(common, ANI,

				"** ch %d: ofdm weak signal: %s=>%s\n",

				chan->channel,

				!aniState->ofdmWeakSigDetectOff ?
@@ -1313,7 +1309,7 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah, 
		u32 level = param;



		if (level >= ARRAY_SIZE(firstep_table)) {

			ath_dbg(common, ATH_DBG_ANI,

			ath_dbg(common, ANI,

				"ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",

				level, ARRAY_SIZE(firstep_table));

			return false;
@@ -1350,7 +1346,7 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah, 
			      AR_PHY_FIND_SIG_FIRSTEP_LOW, value2);



		if (level != aniState->firstepLevel) {

			ath_dbg(common, ATH_DBG_ANI,

			ath_dbg(common, ANI,

				"** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",

				chan->channel,

				aniState->firstepLevel,
@@ -1358,7 +1354,7 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah, 
				ATH9K_ANI_FIRSTEP_LVL_NEW,

				value,

				aniState->iniDef.firstep);

			ath_dbg(common, ATH_DBG_ANI,

			ath_dbg(common, ANI,

				"** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",

				chan->channel,

				aniState->firstepLevel,
@@ -1378,7 +1374,7 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah, 
		u32 level = param;



		if (level >= ARRAY_SIZE(cycpwrThr1_table)) {

			ath_dbg(common, ATH_DBG_ANI,

			ath_dbg(common, ANI,

				"ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",

				level, ARRAY_SIZE(cycpwrThr1_table));

			return false;
@@ -1414,7 +1410,7 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah, 
			      AR_PHY_EXT_TIMING5_CYCPWR_THR1, value2);



		if (level != aniState->spurImmunityLevel) {

			ath_dbg(common, ATH_DBG_ANI,

			ath_dbg(common, ANI,

				"** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",

				chan->channel,

				aniState->spurImmunityLevel,
@@ -1422,7 +1418,7 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah, 
				ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,

				value,

				aniState->iniDef.cycpwrThr1);

			ath_dbg(common, ATH_DBG_ANI,

			ath_dbg(common, ANI,

				"** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",

				chan->channel,

				aniState->spurImmunityLevel,
@@ -1448,11 +1444,11 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah, 
	case ATH9K_ANI_PRESENT:

		break;

	default:

		ath_dbg(common, ATH_DBG_ANI, "invalid cmd %u\n", cmd);

		ath_dbg(common, ANI, "invalid cmd %u\n", cmd);

		return false;

	}



	ath_dbg(common, ATH_DBG_ANI,

	ath_dbg(common, ANI,

		"ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",

		aniState->spurImmunityLevel,

		!aniState->ofdmWeakSigDetectOff ? "on" : "off",
@@ -1506,7 +1502,7 @@ static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah) 


	iniDef = &aniState->iniDef;



	ath_dbg(common, ATH_DBG_ANI, "ver %d.%d opmode %u chan %d Mhz/0x%x\n",

	ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz/0x%x\n",

		ah->hw_version.macVersion,

		ah->hw_version.macRev,

		ah->opmode,

drivers/net/wireless/ath/ath9k/ar9002_calib.c

+61 −73
Original line number Diff line number Diff line
@@ -61,18 +61,16 @@ static void ar9002_hw_setup_calibration(struct ath_hw *ah, 
	switch (currCal->calData->calType) {

	case IQ_MISMATCH_CAL:

		REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);

		ath_dbg(common, ATH_DBG_CALIBRATE,

		ath_dbg(common, CALIBRATE,

			"starting IQ Mismatch Calibration\n");

		break;

	case ADC_GAIN_CAL:

		REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);

		ath_dbg(common, ATH_DBG_CALIBRATE,

			"starting ADC Gain Calibration\n");

		ath_dbg(common, CALIBRATE, "starting ADC Gain Calibration\n");

		break;

	case ADC_DC_CAL:

		REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);

		ath_dbg(common, ATH_DBG_CALIBRATE,

			"starting ADC DC Calibration\n");

		ath_dbg(common, CALIBRATE, "starting ADC DC Calibration\n");

		break;

	}
@@ -129,7 +127,7 @@ static void ar9002_hw_iqcal_collect(struct ath_hw *ah) 
			REG_READ(ah, AR_PHY_CAL_MEAS_1(i));

		ah->totalIqCorrMeas[i] +=

			(int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));

		ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,

		ath_dbg(ath9k_hw_common(ah), CALIBRATE,

			"%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",

			ah->cal_samples, i, ah->totalPowerMeasI[i],

			ah->totalPowerMeasQ[i],
@@ -151,7 +149,7 @@ static void ar9002_hw_adc_gaincal_collect(struct ath_hw *ah) 
		ah->totalAdcQEvenPhase[i] +=

			REG_READ(ah, AR_PHY_CAL_MEAS_3(i));



		ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,

		ath_dbg(ath9k_hw_common(ah), CALIBRATE,

			"%d: Chn %d oddi=0x%08x; eveni=0x%08x; oddq=0x%08x; evenq=0x%08x;\n",

			ah->cal_samples, i,

			ah->totalAdcIOddPhase[i],
@@ -175,7 +173,7 @@ static void ar9002_hw_adc_dccal_collect(struct ath_hw *ah) 
		ah->totalAdcDcOffsetQEvenPhase[i] +=

			(int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));



		ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,

		ath_dbg(ath9k_hw_common(ah), CALIBRATE,

			"%d: Chn %d oddi=0x%08x; eveni=0x%08x; oddq=0x%08x; evenq=0x%08x;\n",

			ah->cal_samples, i,

			ah->totalAdcDcOffsetIOddPhase[i],
@@ -198,11 +196,11 @@ static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) 
		powerMeasQ = ah->totalPowerMeasQ[i];

		iqCorrMeas = ah->totalIqCorrMeas[i];



		ath_dbg(common, ATH_DBG_CALIBRATE,

		ath_dbg(common, CALIBRATE,

			"Starting IQ Cal and Correction for Chain %d\n",

			i);



		ath_dbg(common, ATH_DBG_CALIBRATE,

		ath_dbg(common, CALIBRATE,

			"Original: Chn %d iq_corr_meas = 0x%08x\n",

			i, ah->totalIqCorrMeas[i]);
@@ -213,12 +211,11 @@ static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) 
			iqCorrNeg = 1;

		}



		ath_dbg(common, ATH_DBG_CALIBRATE,

			"Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);

		ath_dbg(common, ATH_DBG_CALIBRATE,

			"Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);

		ath_dbg(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",

			iqCorrNeg);

		ath_dbg(common, CALIBRATE, "Chn %d pwr_meas_i = 0x%08x\n",

			i, powerMeasI);

		ath_dbg(common, CALIBRATE, "Chn %d pwr_meas_q = 0x%08x\n",

			i, powerMeasQ);

		ath_dbg(common, CALIBRATE, "iqCorrNeg is 0x%08x\n", iqCorrNeg);



		iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;

		qCoffDenom = powerMeasQ / 64;
@@ -227,13 +224,13 @@ static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) 
		    (qCoffDenom != 0)) {

			iCoff = iqCorrMeas / iCoffDenom;

			qCoff = powerMeasI / qCoffDenom - 64;

			ath_dbg(common, ATH_DBG_CALIBRATE,

				"Chn %d iCoff = 0x%08x\n", i, iCoff);

			ath_dbg(common, ATH_DBG_CALIBRATE,

				"Chn %d qCoff = 0x%08x\n", i, qCoff);

			ath_dbg(common, CALIBRATE, "Chn %d iCoff = 0x%08x\n",

				i, iCoff);

			ath_dbg(common, CALIBRATE, "Chn %d qCoff = 0x%08x\n",

				i, qCoff);



			iCoff = iCoff & 0x3f;

			ath_dbg(common, ATH_DBG_CALIBRATE,

			ath_dbg(common, CALIBRATE,

				"New: Chn %d iCoff = 0x%08x\n", i, iCoff);

			if (iqCorrNeg == 0x0)

				iCoff = 0x40 - iCoff;
@@ -243,7 +240,7 @@ static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) 
			else if (qCoff <= -16)

				qCoff = -16;



			ath_dbg(common, ATH_DBG_CALIBRATE,

			ath_dbg(common, CALIBRATE,

				"Chn %d : iCoff = 0x%x  qCoff = 0x%x\n",

				i, iCoff, qCoff);
@@ -253,7 +250,7 @@ static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) 
			REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),

				      AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,

				      qCoff);

			ath_dbg(common, ATH_DBG_CALIBRATE,

			ath_dbg(common, CALIBRATE,

				"IQ Cal and Correction done for Chain %d\n",

				i);

		}
@@ -275,21 +272,17 @@ static void ar9002_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains) 
		qOddMeasOffset = ah->totalAdcQOddPhase[i];

		qEvenMeasOffset = ah->totalAdcQEvenPhase[i];



		ath_dbg(common, ATH_DBG_CALIBRATE,

		ath_dbg(common, CALIBRATE,

			"Starting ADC Gain Cal for Chain %d\n", i);



		ath_dbg(common, ATH_DBG_CALIBRATE,

			"Chn %d pwr_meas_odd_i = 0x%08x\n", i,

			iOddMeasOffset);

		ath_dbg(common, ATH_DBG_CALIBRATE,

			"Chn %d pwr_meas_even_i = 0x%08x\n", i,

			iEvenMeasOffset);

		ath_dbg(common, ATH_DBG_CALIBRATE,

			"Chn %d pwr_meas_odd_q = 0x%08x\n", i,

			qOddMeasOffset);

		ath_dbg(common, ATH_DBG_CALIBRATE,

			"Chn %d pwr_meas_even_q = 0x%08x\n", i,

			qEvenMeasOffset);

		ath_dbg(common, CALIBRATE, "Chn %d pwr_meas_odd_i = 0x%08x\n",

			i, iOddMeasOffset);

		ath_dbg(common, CALIBRATE, "Chn %d pwr_meas_even_i = 0x%08x\n",

			i, iEvenMeasOffset);

		ath_dbg(common, CALIBRATE, "Chn %d pwr_meas_odd_q = 0x%08x\n",

			i, qOddMeasOffset);

		ath_dbg(common, CALIBRATE, "Chn %d pwr_meas_even_q = 0x%08x\n",

			i, qEvenMeasOffset);



		if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {

			iGainMismatch =
@@ -299,19 +292,19 @@ static void ar9002_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains) 
				((qOddMeasOffset * 32) /

				 qEvenMeasOffset) & 0x3f;



			ath_dbg(common, ATH_DBG_CALIBRATE,

				"Chn %d gain_mismatch_i = 0x%08x\n", i,

				iGainMismatch);

			ath_dbg(common, ATH_DBG_CALIBRATE,

				"Chn %d gain_mismatch_q = 0x%08x\n", i,

				qGainMismatch);

			ath_dbg(common, CALIBRATE,

				"Chn %d gain_mismatch_i = 0x%08x\n",

				i, iGainMismatch);

			ath_dbg(common, CALIBRATE,

				"Chn %d gain_mismatch_q = 0x%08x\n",

				i, qGainMismatch);



			val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));

			val &= 0xfffff000;

			val |= (qGainMismatch) | (iGainMismatch << 6);

			REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);



			ath_dbg(common, ATH_DBG_CALIBRATE,

			ath_dbg(common, CALIBRATE,

				"ADC Gain Cal done for Chain %d\n", i);

		}

	}
@@ -337,40 +330,36 @@ static void ar9002_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains) 
		qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i];

		qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i];



		ath_dbg(common, ATH_DBG_CALIBRATE,

		ath_dbg(common, CALIBRATE,

			"Starting ADC DC Offset Cal for Chain %d\n", i);



		ath_dbg(common, ATH_DBG_CALIBRATE,

			"Chn %d pwr_meas_odd_i = %d\n", i,

			iOddMeasOffset);

		ath_dbg(common, ATH_DBG_CALIBRATE,

			"Chn %d pwr_meas_even_i = %d\n", i,

			iEvenMeasOffset);

		ath_dbg(common, ATH_DBG_CALIBRATE,

			"Chn %d pwr_meas_odd_q = %d\n", i,

			qOddMeasOffset);

		ath_dbg(common, ATH_DBG_CALIBRATE,

			"Chn %d pwr_meas_even_q = %d\n", i,

			qEvenMeasOffset);

		ath_dbg(common, CALIBRATE, "Chn %d pwr_meas_odd_i = %d\n",

			i, iOddMeasOffset);

		ath_dbg(common, CALIBRATE, "Chn %d pwr_meas_even_i = %d\n",

			i, iEvenMeasOffset);

		ath_dbg(common, CALIBRATE, "Chn %d pwr_meas_odd_q = %d\n",

			i, qOddMeasOffset);

		ath_dbg(common, CALIBRATE, "Chn %d pwr_meas_even_q = %d\n",

			i, qEvenMeasOffset);



		iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /

			       numSamples) & 0x1ff;

		qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /

			       numSamples) & 0x1ff;



		ath_dbg(common, ATH_DBG_CALIBRATE,

			"Chn %d dc_offset_mismatch_i = 0x%08x\n", i,

			iDcMismatch);

		ath_dbg(common, ATH_DBG_CALIBRATE,

			"Chn %d dc_offset_mismatch_q = 0x%08x\n", i,

			qDcMismatch);

		ath_dbg(common, CALIBRATE,

			"Chn %d dc_offset_mismatch_i = 0x%08x\n",

			i, iDcMismatch);

		ath_dbg(common, CALIBRATE,

			"Chn %d dc_offset_mismatch_q = 0x%08x\n",

			i, qDcMismatch);



		val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));

		val &= 0xc0000fff;

		val |= (qDcMismatch << 12) | (iDcMismatch << 21);

		REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);



		ath_dbg(common, ATH_DBG_CALIBRATE,

		ath_dbg(common, CALIBRATE,

			"ADC DC Offset Cal done for Chain %d\n", i);

	}
@@ -560,7 +549,7 @@ static inline void ar9285_hw_pa_cal(struct ath_hw *ah, bool is_reset) 
		{ 0x7838, 0 },

	};



	ath_dbg(common, ATH_DBG_CALIBRATE, "Running PA Calibration\n");

	ath_dbg(common, CALIBRATE, "Running PA Calibration\n");



	/* PA CAL is not needed for high power solution */

	if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) ==
@@ -741,7 +730,7 @@ static bool ar9285_hw_cl_cal(struct ath_hw *ah, struct ath9k_channel *chan) 
		REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);

		if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,

				  AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) {

			ath_dbg(common, ATH_DBG_CALIBRATE,

			ath_dbg(common, CALIBRATE,

				"offset calibration failed to complete in 1ms; noisy environment?\n");

			return false;

		}
@@ -755,7 +744,7 @@ static bool ar9285_hw_cl_cal(struct ath_hw *ah, struct ath9k_channel *chan) 
	REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);

	if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,

			  0, AH_WAIT_TIMEOUT)) {

		ath_dbg(common, ATH_DBG_CALIBRATE,

		ath_dbg(common, CALIBRATE,

			"offset calibration failed to complete in 1ms; noisy environment?\n");

		return false;

	}
@@ -851,7 +840,7 @@ static bool ar9002_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan) 
		if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,

				   AR_PHY_AGC_CONTROL_CAL,

				   0, AH_WAIT_TIMEOUT)) {

			ath_dbg(common, ATH_DBG_CALIBRATE,

			ath_dbg(common, CALIBRATE,

				"offset calibration failed to complete in 1ms; noisy environment?\n");

			return false;

		}
@@ -886,22 +875,21 @@ static bool ar9002_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan) 
		if (ar9002_hw_is_cal_supported(ah, chan, ADC_GAIN_CAL)) {

			INIT_CAL(&ah->adcgain_caldata);

			INSERT_CAL(ah, &ah->adcgain_caldata);

			ath_dbg(common, ATH_DBG_CALIBRATE,

					"enabling ADC Gain Calibration.\n");

			ath_dbg(common, CALIBRATE,

					"enabling ADC Gain Calibration\n");

		}



		if (ar9002_hw_is_cal_supported(ah, chan, ADC_DC_CAL)) {

			INIT_CAL(&ah->adcdc_caldata);

			INSERT_CAL(ah, &ah->adcdc_caldata);

			ath_dbg(common, ATH_DBG_CALIBRATE,

					"enabling ADC DC Calibration.\n");

			ath_dbg(common, CALIBRATE,

					"enabling ADC DC Calibration\n");

		}



		if (ar9002_hw_is_cal_supported(ah, chan, IQ_MISMATCH_CAL)) {

			INIT_CAL(&ah->iq_caldata);

			INSERT_CAL(ah, &ah->iq_caldata);

			ath_dbg(common, ATH_DBG_CALIBRATE,

					"enabling IQ Calibration.\n");

			ath_dbg(common, CALIBRATE, "enabling IQ Calibration\n");

		}



		ah->cal_list_curr = ah->cal_list;

drivers/net/wireless/ath/ath9k/ar9002_mac.c

+5 −5
Original line number Diff line number Diff line
@@ -107,7 +107,7 @@ static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked) 
		}



		if (isr & AR_ISR_RXORN) {

			ath_dbg(common, ATH_DBG_INTERRUPT,

			ath_dbg(common, INTERRUPT,

				"receive FIFO overrun interrupt\n");

		}
@@ -143,24 +143,24 @@ static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked) 


		if (fatal_int) {

			if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {

				ath_dbg(common, ATH_DBG_ANY,

				ath_dbg(common, ANY,

					"received PCI FATAL interrupt\n");

			}

			if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {

				ath_dbg(common, ATH_DBG_ANY,

				ath_dbg(common, ANY,

					"received PCI PERR interrupt\n");

			}

			*masked |= ATH9K_INT_FATAL;

		}

		if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {

			ath_dbg(common, ATH_DBG_INTERRUPT,

			ath_dbg(common, INTERRUPT,

				"AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");

			REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);

			REG_WRITE(ah, AR_RC, 0);

			*masked |= ATH9K_INT_FATAL;

		}

		if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {

			ath_dbg(common, ATH_DBG_INTERRUPT,

			ath_dbg(common, INTERRUPT,

				"AR_INTR_SYNC_LOCAL_TIMEOUT\n");

		}