Loading arch/tile/include/arch/Kbuild +0 −17 Original line number Diff line number Diff line header-y += abi.h header-y += chip.h header-y += chip_tile64.h header-y += chip_tilegx.h header-y += chip_tilepro.h header-y += icache.h header-y += interrupts.h header-y += interrupts_32.h header-y += interrupts_64.h header-y += opcode.h header-y += opcode_tilegx.h header-y += opcode_tilepro.h header-y += sim.h header-y += sim_def.h header-y += spr_def.h header-y += spr_def_32.h header-y += spr_def_64.h arch/tile/include/arch/spr_def.h +4 −8 Original line number Diff line number Diff line Loading @@ -11,15 +11,11 @@ * NON INFRINGEMENT. See the GNU General Public License for * more details. */ #ifndef __ARCH_SPR_DEF_H__ #define __ARCH_SPR_DEF_H__ /* Include the proper base SPR definition file. */ #ifdef __tilegx__ #include <arch/spr_def_64.h> #else #include <arch/spr_def_32.h> #endif #include <uapi/arch/spr_def.h> #ifdef __KERNEL__ /* * In addition to including the proper base SPR definition file, depending Loading Loading @@ -110,4 +106,4 @@ #define INT_INTCTRL_K \ _concat4(INT_INTCTRL_, CONFIG_KERNEL_PL,,) #endif /* __KERNEL__ */ #endif /* __ARCH_SPR_DEF_H__ */ arch/tile/include/asm/Kbuild +0 −3 Original line number Diff line number Diff line include include/asm-generic/Kbuild.asm header-y += ../arch/ header-y += cachectl.h header-y += ucontext.h header-y += hardwall.h generic-y += bug.h generic-y += bugs.h Loading arch/tile/include/asm/hardwall.h +1 −32 Original line number Diff line number Diff line Loading @@ -14,40 +14,11 @@ * Provide methods for access control of per-cpu resources like * UDN, IDN, or IPI. */ #ifndef _ASM_TILE_HARDWALL_H #define _ASM_TILE_HARDWALL_H #include <arch/chip.h> #include <linux/ioctl.h> #define HARDWALL_IOCTL_BASE 0xa2 /* * The HARDWALL_CREATE() ioctl is a macro with a "size" argument. * The resulting ioctl value is passed to the kernel in conjunction * with a pointer to a standard kernel bitmask of cpus. * For network resources (UDN or IDN) the bitmask must physically * represent a rectangular configuration on the chip. * The "size" is the number of bytes of cpu mask data. */ #define _HARDWALL_CREATE 1 #define HARDWALL_CREATE(size) \ _IOC(_IOC_READ, HARDWALL_IOCTL_BASE, _HARDWALL_CREATE, (size)) #define _HARDWALL_ACTIVATE 2 #define HARDWALL_ACTIVATE \ _IO(HARDWALL_IOCTL_BASE, _HARDWALL_ACTIVATE) #define _HARDWALL_DEACTIVATE 3 #define HARDWALL_DEACTIVATE \ _IO(HARDWALL_IOCTL_BASE, _HARDWALL_DEACTIVATE) #define _HARDWALL_GET_ID 4 #define HARDWALL_GET_ID \ _IO(HARDWALL_IOCTL_BASE, _HARDWALL_GET_ID) #include <uapi/asm/hardwall.h> #ifdef __KERNEL__ /* /proc hooks for hardwall. */ struct proc_dir_entry; #ifdef CONFIG_HARDWALL Loading @@ -56,6 +27,4 @@ int proc_pid_hardwall(struct task_struct *task, char *buffer); #else static inline void proc_tile_hardwall_init(struct proc_dir_entry *root) {} #endif #endif #endif /* _ASM_TILE_HARDWALL_H */ arch/tile/include/asm/ptrace.h +2 −70 Original line number Diff line number Diff line Loading @@ -11,87 +11,21 @@ * NON INFRINGEMENT. See the GNU General Public License for * more details. */ #ifndef _ASM_TILE_PTRACE_H #define _ASM_TILE_PTRACE_H #include <arch/chip.h> #include <arch/abi.h> /* These must match struct pt_regs, below. */ #if CHIP_WORD_SIZE() == 32 #define PTREGS_OFFSET_REG(n) ((n)*4) #else #define PTREGS_OFFSET_REG(n) ((n)*8) #endif #define PTREGS_OFFSET_BASE 0 #define PTREGS_OFFSET_TP PTREGS_OFFSET_REG(53) #define PTREGS_OFFSET_SP PTREGS_OFFSET_REG(54) #define PTREGS_OFFSET_LR PTREGS_OFFSET_REG(55) #define PTREGS_NR_GPRS 56 #define PTREGS_OFFSET_PC PTREGS_OFFSET_REG(56) #define PTREGS_OFFSET_EX1 PTREGS_OFFSET_REG(57) #define PTREGS_OFFSET_FAULTNUM PTREGS_OFFSET_REG(58) #define PTREGS_OFFSET_ORIG_R0 PTREGS_OFFSET_REG(59) #define PTREGS_OFFSET_FLAGS PTREGS_OFFSET_REG(60) #if CHIP_HAS_CMPEXCH() #define PTREGS_OFFSET_CMPEXCH PTREGS_OFFSET_REG(61) #endif #define PTREGS_SIZE PTREGS_OFFSET_REG(64) #include <linux/compiler.h> #ifndef __ASSEMBLY__ #ifdef __KERNEL__ /* Benefit from consistent use of "long" on all chips. */ typedef unsigned long pt_reg_t; #else /* Provide appropriate length type to userspace regardless of -m32/-m64. */ typedef uint_reg_t pt_reg_t; #endif /* * This struct defines the way the registers are stored on the stack during a * system call or exception. "struct sigcontext" has the same shape. */ struct pt_regs { /* Saved main processor registers; 56..63 are special. */ /* tp, sp, and lr must immediately follow regs[] for aliasing. */ pt_reg_t regs[53]; pt_reg_t tp; /* aliases regs[TREG_TP] */ pt_reg_t sp; /* aliases regs[TREG_SP] */ pt_reg_t lr; /* aliases regs[TREG_LR] */ /* Saved special registers. */ pt_reg_t pc; /* stored in EX_CONTEXT_K_0 */ pt_reg_t ex1; /* stored in EX_CONTEXT_K_1 (PL and ICS bit) */ pt_reg_t faultnum; /* fault number (INT_SWINT_1 for syscall) */ pt_reg_t orig_r0; /* r0 at syscall entry, else zero */ pt_reg_t flags; /* flags (see below) */ #if !CHIP_HAS_CMPEXCH() pt_reg_t pad[3]; #else pt_reg_t cmpexch; /* value of CMPEXCH_VALUE SPR at interrupt */ pt_reg_t pad[2]; #endif }; #endif /* __ASSEMBLY__ */ #define PTRACE_GETREGS 12 #define PTRACE_SETREGS 13 #define PTRACE_GETFPREGS 14 #define PTRACE_SETFPREGS 15 #include <uapi/asm/ptrace.h> /* Support TILE-specific ptrace options, with events starting at 16. */ #define PTRACE_O_TRACEMIGRATE 0x00010000 #define PTRACE_EVENT_MIGRATE 16 #ifdef __KERNEL__ #define PTRACE_O_MASK_TILE (PTRACE_O_TRACEMIGRATE) #define PT_TRACE_MIGRATE 0x00080000 #define PT_TRACE_MASK_TILE (PT_TRACE_MIGRATE) #endif #ifdef __KERNEL__ /* Flag bits in pt_regs.flags */ #define PT_FLAGS_DISABLE_IRQ 1 /* on return to kernel, disable irqs */ Loading Loading @@ -159,6 +93,4 @@ extern void send_sigtrap(struct task_struct *tsk, struct pt_regs *regs, #define SINGLESTEP_STATE_TARGET_LB 2 #define SINGLESTEP_STATE_TARGET_UB 7 #endif /* !__KERNEL__ */ #endif /* _ASM_TILE_PTRACE_H */ Loading
arch/tile/include/arch/Kbuild +0 −17 Original line number Diff line number Diff line header-y += abi.h header-y += chip.h header-y += chip_tile64.h header-y += chip_tilegx.h header-y += chip_tilepro.h header-y += icache.h header-y += interrupts.h header-y += interrupts_32.h header-y += interrupts_64.h header-y += opcode.h header-y += opcode_tilegx.h header-y += opcode_tilepro.h header-y += sim.h header-y += sim_def.h header-y += spr_def.h header-y += spr_def_32.h header-y += spr_def_64.h
arch/tile/include/arch/spr_def.h +4 −8 Original line number Diff line number Diff line Loading @@ -11,15 +11,11 @@ * NON INFRINGEMENT. See the GNU General Public License for * more details. */ #ifndef __ARCH_SPR_DEF_H__ #define __ARCH_SPR_DEF_H__ /* Include the proper base SPR definition file. */ #ifdef __tilegx__ #include <arch/spr_def_64.h> #else #include <arch/spr_def_32.h> #endif #include <uapi/arch/spr_def.h> #ifdef __KERNEL__ /* * In addition to including the proper base SPR definition file, depending Loading Loading @@ -110,4 +106,4 @@ #define INT_INTCTRL_K \ _concat4(INT_INTCTRL_, CONFIG_KERNEL_PL,,) #endif /* __KERNEL__ */ #endif /* __ARCH_SPR_DEF_H__ */
arch/tile/include/asm/Kbuild +0 −3 Original line number Diff line number Diff line include include/asm-generic/Kbuild.asm header-y += ../arch/ header-y += cachectl.h header-y += ucontext.h header-y += hardwall.h generic-y += bug.h generic-y += bugs.h Loading
arch/tile/include/asm/hardwall.h +1 −32 Original line number Diff line number Diff line Loading @@ -14,40 +14,11 @@ * Provide methods for access control of per-cpu resources like * UDN, IDN, or IPI. */ #ifndef _ASM_TILE_HARDWALL_H #define _ASM_TILE_HARDWALL_H #include <arch/chip.h> #include <linux/ioctl.h> #define HARDWALL_IOCTL_BASE 0xa2 /* * The HARDWALL_CREATE() ioctl is a macro with a "size" argument. * The resulting ioctl value is passed to the kernel in conjunction * with a pointer to a standard kernel bitmask of cpus. * For network resources (UDN or IDN) the bitmask must physically * represent a rectangular configuration on the chip. * The "size" is the number of bytes of cpu mask data. */ #define _HARDWALL_CREATE 1 #define HARDWALL_CREATE(size) \ _IOC(_IOC_READ, HARDWALL_IOCTL_BASE, _HARDWALL_CREATE, (size)) #define _HARDWALL_ACTIVATE 2 #define HARDWALL_ACTIVATE \ _IO(HARDWALL_IOCTL_BASE, _HARDWALL_ACTIVATE) #define _HARDWALL_DEACTIVATE 3 #define HARDWALL_DEACTIVATE \ _IO(HARDWALL_IOCTL_BASE, _HARDWALL_DEACTIVATE) #define _HARDWALL_GET_ID 4 #define HARDWALL_GET_ID \ _IO(HARDWALL_IOCTL_BASE, _HARDWALL_GET_ID) #include <uapi/asm/hardwall.h> #ifdef __KERNEL__ /* /proc hooks for hardwall. */ struct proc_dir_entry; #ifdef CONFIG_HARDWALL Loading @@ -56,6 +27,4 @@ int proc_pid_hardwall(struct task_struct *task, char *buffer); #else static inline void proc_tile_hardwall_init(struct proc_dir_entry *root) {} #endif #endif #endif /* _ASM_TILE_HARDWALL_H */
arch/tile/include/asm/ptrace.h +2 −70 Original line number Diff line number Diff line Loading @@ -11,87 +11,21 @@ * NON INFRINGEMENT. See the GNU General Public License for * more details. */ #ifndef _ASM_TILE_PTRACE_H #define _ASM_TILE_PTRACE_H #include <arch/chip.h> #include <arch/abi.h> /* These must match struct pt_regs, below. */ #if CHIP_WORD_SIZE() == 32 #define PTREGS_OFFSET_REG(n) ((n)*4) #else #define PTREGS_OFFSET_REG(n) ((n)*8) #endif #define PTREGS_OFFSET_BASE 0 #define PTREGS_OFFSET_TP PTREGS_OFFSET_REG(53) #define PTREGS_OFFSET_SP PTREGS_OFFSET_REG(54) #define PTREGS_OFFSET_LR PTREGS_OFFSET_REG(55) #define PTREGS_NR_GPRS 56 #define PTREGS_OFFSET_PC PTREGS_OFFSET_REG(56) #define PTREGS_OFFSET_EX1 PTREGS_OFFSET_REG(57) #define PTREGS_OFFSET_FAULTNUM PTREGS_OFFSET_REG(58) #define PTREGS_OFFSET_ORIG_R0 PTREGS_OFFSET_REG(59) #define PTREGS_OFFSET_FLAGS PTREGS_OFFSET_REG(60) #if CHIP_HAS_CMPEXCH() #define PTREGS_OFFSET_CMPEXCH PTREGS_OFFSET_REG(61) #endif #define PTREGS_SIZE PTREGS_OFFSET_REG(64) #include <linux/compiler.h> #ifndef __ASSEMBLY__ #ifdef __KERNEL__ /* Benefit from consistent use of "long" on all chips. */ typedef unsigned long pt_reg_t; #else /* Provide appropriate length type to userspace regardless of -m32/-m64. */ typedef uint_reg_t pt_reg_t; #endif /* * This struct defines the way the registers are stored on the stack during a * system call or exception. "struct sigcontext" has the same shape. */ struct pt_regs { /* Saved main processor registers; 56..63 are special. */ /* tp, sp, and lr must immediately follow regs[] for aliasing. */ pt_reg_t regs[53]; pt_reg_t tp; /* aliases regs[TREG_TP] */ pt_reg_t sp; /* aliases regs[TREG_SP] */ pt_reg_t lr; /* aliases regs[TREG_LR] */ /* Saved special registers. */ pt_reg_t pc; /* stored in EX_CONTEXT_K_0 */ pt_reg_t ex1; /* stored in EX_CONTEXT_K_1 (PL and ICS bit) */ pt_reg_t faultnum; /* fault number (INT_SWINT_1 for syscall) */ pt_reg_t orig_r0; /* r0 at syscall entry, else zero */ pt_reg_t flags; /* flags (see below) */ #if !CHIP_HAS_CMPEXCH() pt_reg_t pad[3]; #else pt_reg_t cmpexch; /* value of CMPEXCH_VALUE SPR at interrupt */ pt_reg_t pad[2]; #endif }; #endif /* __ASSEMBLY__ */ #define PTRACE_GETREGS 12 #define PTRACE_SETREGS 13 #define PTRACE_GETFPREGS 14 #define PTRACE_SETFPREGS 15 #include <uapi/asm/ptrace.h> /* Support TILE-specific ptrace options, with events starting at 16. */ #define PTRACE_O_TRACEMIGRATE 0x00010000 #define PTRACE_EVENT_MIGRATE 16 #ifdef __KERNEL__ #define PTRACE_O_MASK_TILE (PTRACE_O_TRACEMIGRATE) #define PT_TRACE_MIGRATE 0x00080000 #define PT_TRACE_MASK_TILE (PT_TRACE_MIGRATE) #endif #ifdef __KERNEL__ /* Flag bits in pt_regs.flags */ #define PT_FLAGS_DISABLE_IRQ 1 /* on return to kernel, disable irqs */ Loading Loading @@ -159,6 +93,4 @@ extern void send_sigtrap(struct task_struct *tsk, struct pt_regs *regs, #define SINGLESTEP_STATE_TARGET_LB 2 #define SINGLESTEP_STATE_TARGET_UB 7 #endif /* !__KERNEL__ */ #endif /* _ASM_TILE_PTRACE_H */