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Commit d1f0690a authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "Merge android-4.9.127 (be4935d5) into msm-4.9"

parents fa42a652 ad6c3ffb
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VERSION = 4
PATCHLEVEL = 9
SUBLEVEL = 126
SUBLEVEL = 127
EXTRAVERSION =
NAME = Roaring Lionus

+0 −2
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@@ -271,7 +271,6 @@ CONFIG_USB_STORAGE=y
CONFIG_USB_CHIPIDEA=y
CONFIG_USB_CHIPIDEA_UDC=y
CONFIG_USB_CHIPIDEA_HOST=y
CONFIG_USB_CHIPIDEA_ULPI=y
CONFIG_USB_SERIAL=m
CONFIG_USB_SERIAL_GENERIC=y
CONFIG_USB_SERIAL_FTDI_SIO=m
@@ -308,7 +307,6 @@ CONFIG_USB_GADGETFS=m
CONFIG_USB_FUNCTIONFS=m
CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_ULPI_BUS=y
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
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@@ -16,6 +16,7 @@ config ARCH_ROCKCHIP
	select ROCKCHIP_TIMER
	select ARM_GLOBAL_TIMER
	select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
	select PM
	help
	  Support for Rockchip's Cortex-A9 Single-to-Quad-Core-SoCs
	  containing the RK2928, RK30xx and RK31xx series.
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@@ -237,6 +237,7 @@ config ARCH_ROCKCHIP
	select GPIOLIB
	select PINCTRL
	select PINCTRL_ROCKCHIP
	select PM
	select ROCKCHIP_TIMER
	help
	  This enables support for the ARMv8 based Rockchip chipsets,
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@@ -22,6 +22,11 @@
#define CTR_L1IP_MASK		3
#define CTR_CWG_SHIFT		24
#define CTR_CWG_MASK		15
#define CTR_DMINLINE_SHIFT	16
#define CTR_IMINLINE_SHIFT	0

#define CTR_CACHE_MINLINE_MASK	\
	((0xf << CTR_DMINLINE_SHIFT) | (0xf << CTR_IMINLINE_SHIFT))

#define ICACHE_POLICY_RESERVED	0
#define ICACHE_POLICY_AIVIVT	1
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