Loading drivers/gpu/drm/msm/sde/sde_hw_cdm.c +18 −0 Original line number Diff line number Diff line Loading @@ -56,6 +56,19 @@ static u32 cosite_v_coeff[] = {0x00080004}; */ static u32 offsite_v_coeff[] = {0x00060002}; /* Limited Range rgb2yuv coeff with clamp and bias values for CSC 10 module */ static struct sde_csc_cfg rgb2yuv_cfg = { { 0x0083, 0x0102, 0x0032, 0x1fb5, 0x1f6c, 0x00e1, 0x00e1, 0x1f45, 0x1fdc }, { 0x00, 0x00, 0x00 }, { 0x0040, 0x0200, 0x0200 }, { 0x000, 0x3ff, 0x000, 0x3ff, 0x000, 0x3ff }, { 0x040, 0x3ac, 0x040, 0x3c0, 0x040, 0x3c0 }, }; static struct sde_cdm_cfg *_cdm_offset(enum sde_cdm cdm, struct sde_mdss_cfg *m, void __iomem *addr, Loading Loading @@ -279,6 +292,11 @@ struct sde_hw_cdm *sde_hw_cdm_init(enum sde_cdm idx, sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->name, c->hw.blk_off, c->hw.blk_off + c->hw.length, c->hw.xin_id); /* * Perform any default initialization for the chroma down module * @setup default csc coefficients */ sde_hw_cdm_setup_csc_10bit(c, &rgb2yuv_cfg); return c; } Loading drivers/gpu/drm/msm/sde/sde_hw_interrupts.c +10 −0 Original line number Diff line number Diff line Loading @@ -844,11 +844,21 @@ static int sde_hw_intr_disable_irq(struct sde_hw_intr *intr, int irq_idx) static int sde_hw_intr_clear_irqs(struct sde_hw_intr *intr) { int i; for (i = 0; i < ARRAY_SIZE(sde_intr_set); i++) SDE_REG_WRITE(&intr->hw, sde_intr_set[i].clr_off, 0xffffffff); return 0; } static int sde_hw_intr_disable_irqs(struct sde_hw_intr *intr) { int i; for (i = 0; i < ARRAY_SIZE(sde_intr_set); i++) SDE_REG_WRITE(&intr->hw, sde_intr_set[i].en_off, 0x00000000); return 0; } Loading drivers/gpu/drm/msm/sde/sde_kms.c +1 −1 Original line number Diff line number Diff line Loading @@ -1226,7 +1226,7 @@ static const struct msm_kms_funcs kms_funcs = { /* the caller api needs to turn on clock before calling it */ static inline void _sde_kms_core_hw_rev_init(struct sde_kms *sde_kms) { return; sde_kms->core_rev = readl_relaxed(sde_kms->mmio + 0x0); } static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms) Loading Loading
drivers/gpu/drm/msm/sde/sde_hw_cdm.c +18 −0 Original line number Diff line number Diff line Loading @@ -56,6 +56,19 @@ static u32 cosite_v_coeff[] = {0x00080004}; */ static u32 offsite_v_coeff[] = {0x00060002}; /* Limited Range rgb2yuv coeff with clamp and bias values for CSC 10 module */ static struct sde_csc_cfg rgb2yuv_cfg = { { 0x0083, 0x0102, 0x0032, 0x1fb5, 0x1f6c, 0x00e1, 0x00e1, 0x1f45, 0x1fdc }, { 0x00, 0x00, 0x00 }, { 0x0040, 0x0200, 0x0200 }, { 0x000, 0x3ff, 0x000, 0x3ff, 0x000, 0x3ff }, { 0x040, 0x3ac, 0x040, 0x3c0, 0x040, 0x3c0 }, }; static struct sde_cdm_cfg *_cdm_offset(enum sde_cdm cdm, struct sde_mdss_cfg *m, void __iomem *addr, Loading Loading @@ -279,6 +292,11 @@ struct sde_hw_cdm *sde_hw_cdm_init(enum sde_cdm idx, sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->name, c->hw.blk_off, c->hw.blk_off + c->hw.length, c->hw.xin_id); /* * Perform any default initialization for the chroma down module * @setup default csc coefficients */ sde_hw_cdm_setup_csc_10bit(c, &rgb2yuv_cfg); return c; } Loading
drivers/gpu/drm/msm/sde/sde_hw_interrupts.c +10 −0 Original line number Diff line number Diff line Loading @@ -844,11 +844,21 @@ static int sde_hw_intr_disable_irq(struct sde_hw_intr *intr, int irq_idx) static int sde_hw_intr_clear_irqs(struct sde_hw_intr *intr) { int i; for (i = 0; i < ARRAY_SIZE(sde_intr_set); i++) SDE_REG_WRITE(&intr->hw, sde_intr_set[i].clr_off, 0xffffffff); return 0; } static int sde_hw_intr_disable_irqs(struct sde_hw_intr *intr) { int i; for (i = 0; i < ARRAY_SIZE(sde_intr_set); i++) SDE_REG_WRITE(&intr->hw, sde_intr_set[i].en_off, 0x00000000); return 0; } Loading
drivers/gpu/drm/msm/sde/sde_kms.c +1 −1 Original line number Diff line number Diff line Loading @@ -1226,7 +1226,7 @@ static const struct msm_kms_funcs kms_funcs = { /* the caller api needs to turn on clock before calling it */ static inline void _sde_kms_core_hw_rev_init(struct sde_kms *sde_kms) { return; sde_kms->core_rev = readl_relaxed(sde_kms->mmio + 0x0); } static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms) Loading