Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit d1a6e68c authored by Lina Iyer's avatar Lina Iyer
Browse files

drivers: mailbox: fix control TCS sizing 



Control/hidden TCS hold specific data. Data registers 0 and 1 carry the
PDC wakeup time value. There is no third data register. Fix the TCS
sizing so we write only to the two write-enabled registers.

Change-Id: I83ea3dd843878aa6643ebb266446e00162f729db
Signed-off-by: default avatarLina Iyer <ilina@codeaurora.org>
parent e13b3810

drivers/mailbox/qti-tcs.c

+1 −1
Original line number Diff line number Diff line
@@ -79,7 +79,7 @@ 
#define CMD_STATUS_COMPL		BIT(16)



/* Control/Hidden TCS */

#define TCS_HIDDEN_MAX_SLOTS		3

#define TCS_HIDDEN_MAX_SLOTS		2

#define TCS_HIDDEN_CMD0_DRV_DATA	0x38

#define TCS_HIDDEN_CMD_SHIFT		0x08

drivers/soc/qcom/system_pm.c

+1 −1
Original line number Diff line number Diff line
@@ -24,7 +24,7 @@ static struct rpmh_client *rpmh_client; 


static int setup_wakeup(uint64_t sleep_val)

{

	struct tcs_cmd cmd[3] = { { 0 } };

	struct tcs_cmd cmd[2] = { { 0 } };



	cmd[0].data = (sleep_val >> 32) & PDC_TIME_UPPER_MASK;

	cmd[0].data |= 1 << PDC_TIME_VALID_SHIFT;