Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit d19648d7 authored by Eunbong Song's avatar Eunbong Song Committed by Ralf Baechle
Browse files

MIPS: Octeon: Add PCIe2 support in arch_setup_msi_irq() 



In arch_setup_msi_irq(), there is no case for PCIe2. So board which have PCIe2 functionality
fails to boot with "Kernel panic - not syncing: arch_setup_msi_irq: Invalid octeon_dma_bar_type"
message. This patch solve this problem.

Signed-off-by: default avatarEunbong Song <eunb.song@samsung.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/6747/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent b8bca000

arch/mips/pci/msi-octeon.c

+6 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ 
#include <asm/octeon/cvmx-npi-defs.h>

#include <asm/octeon/cvmx-pci-defs.h>

#include <asm/octeon/cvmx-npei-defs.h>

#include <asm/octeon/cvmx-sli-defs.h>

#include <asm/octeon/cvmx-pexp-defs.h>

#include <asm/octeon/pci-octeon.h>
@@ -162,6 +163,11 @@ int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) 
		msg.address_lo = (0 + CVMX_NPEI_PCIE_MSI_RCV) & 0xffffffff;

		msg.address_hi = (0 + CVMX_NPEI_PCIE_MSI_RCV) >> 32;

		break;

	case OCTEON_DMA_BAR_TYPE_PCIE2:

		/* When using PCIe2, Bar 0 is based at 0 */

		msg.address_lo = (0 + CVMX_SLI_PCIE_MSI_RCV) & 0xffffffff;

		msg.address_hi = (0 + CVMX_SLI_PCIE_MSI_RCV) >> 32;

		break;

	default:

		panic("arch_setup_msi_irq: Invalid octeon_dma_bar_type");

	}