Merge "drm/msm/sde: add ts prefill support to sde plane" into msm-4.9 (d12b0772) · Commits · e / devices / android_kernel_fairphone_FP3

drivers/gpu/drm/msm/msm_drv.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -110,6 +110,8 @@ enum msm_mdp_plane_property {
		PLANE_PROP_ROT_DST_Y,
		PLANE_PROP_ROT_DST_W,
		PLANE_PROP_ROT_DST_H,
		PLANE_PROP_PREFILL_SIZE,
		PLANE_PROP_PREFILL_TIME,

		/* enum/bitmask properties */
		PLANE_PROP_ROTATION,

drivers/gpu/drm/msm/sde/sde_hw_catalog.c

+11 −0

Original line number	Diff line number	Diff line
		@@ -1055,6 +1055,13 @@ static int sde_sspp_parse_dt(struct device_node *np,

		set_bit(SDE_SSPP_SRC, &sspp->features);

		if (sde_cfg->ts_prefill_rev == 1) {
		set_bit(SDE_SSPP_TS_PREFILL, &sspp->features);
		} else if (sde_cfg->ts_prefill_rev == 2) {
		set_bit(SDE_SSPP_TS_PREFILL, &sspp->features);
		set_bit(SDE_SSPP_TS_PREFILL_REC1, &sspp->features);
		}

		sblk->smart_dma_priority =
		PROP_VALUE_ACCESS(prop_value, SSPP_SMART_DMA, i);

		@@ -2584,12 +2591,16 @@ static int _sde_hardware_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev)
		sde_cfg->has_wb_ubwc = true;
		sde_cfg->perf.min_prefill_lines = 25;
		sde_cfg->vbif_qos_nlvl = 4;
		sde_cfg->ts_prefill_rev = 1;
		sde_cfg->perf.min_prefill_lines = 25;
		break;
		case SDE_HW_VER_400:
		/* update sdm845 target here */
		sde_cfg->has_wb_ubwc = true;
		sde_cfg->perf.min_prefill_lines = 24;
		sde_cfg->vbif_qos_nlvl = 8;
		sde_cfg->ts_prefill_rev = 2;
		sde_cfg->perf.min_prefill_lines = 24;
		break;
		default:
		sde_cfg->perf.min_prefill_lines = 0xffff;

drivers/gpu/drm/msm/sde/sde_hw_catalog.h

+6 −0

Original line number	Diff line number	Diff line
		@@ -111,6 +111,8 @@ enum {
		* @SDE_SSPP_SMART_DMA_V1, SmartDMA 1.0 support
		* @SDE_SSPP_SMART_DMA_V2, SmartDMA 2.0 support
		* @SDE_SSPP_SBUF, SSPP support inline stream buffer
		* @SDE_SSPP_TS_PREFILL Supports prefill with traffic shaper
		* @SDE_SSPP_TS_PREFILL_REC1 Supports prefill with traffic shaper multirec
		* @SDE_SSPP_MAX maximum value
		*/
		enum {
		@@ -130,6 +132,8 @@ enum {
		SDE_SSPP_SMART_DMA_V1,
		SDE_SSPP_SMART_DMA_V2,
		SDE_SSPP_SBUF,
		SDE_SSPP_TS_PREFILL,
		SDE_SSPP_TS_PREFILL_REC1,
		SDE_SSPP_MAX
		};

		@@ -763,6 +767,7 @@ struct sde_perf_cfg {
		* @vig_formats Supported formats for vig pipe
		* @wb_formats Supported formats for wb
		* @vbif_qos_nlvl number of vbif QoS priority level
		* @ts_prefill_rev prefill traffic shaper feature revision
		*/
		struct sde_mdss_cfg {
		u32 hwversion;
		@@ -783,6 +788,7 @@ struct sde_mdss_cfg {
		u32 sbuf_headroom;
		bool has_idle_pc;
		u32 vbif_qos_nlvl;
		u32 ts_prefill_rev;

		u32 mdss_count;
		struct sde_mdss_base_cfg mdss[MAX_BLOCKS];

drivers/gpu/drm/msm/sde/sde_hw_sspp.c

+56 −0

Original line number	Diff line number	Diff line
		@@ -79,11 +79,16 @@
		#define SSPP_SW_PIX_EXT_C3_LR 0x120
		#define SSPP_SW_PIX_EXT_C3_TB 0x124
		#define SSPP_SW_PIX_EXT_C3_REQ_PIXELS 0x128
		#define SSPP_TRAFFIC_SHAPER 0x130
		#define SSPP_UBWC_ERROR_STATUS 0x138
		#define SSPP_TRAFFIC_SHAPER_PREFILL 0x150
		#define SSPP_TRAFFIC_SHAPER_REC1_PREFILL 0x154
		#define SSPP_TRAFFIC_SHAPER_REC1 0x158
		#define SSPP_EXCL_REC_SIZE 0x1B4
		#define SSPP_EXCL_REC_XY 0x1B8
		#define SSPP_VIG_OP_MODE 0x0
		#define SSPP_VIG_CSC_10_OP_MODE 0x0
		#define SSPP_TRAFFIC_SHAPER_BPC_MAX 0xFF

		/* SSPP_QOS_CTRL */
		#define SSPP_QOS_CTRL_VBLANK_EN BIT(16)
		@@ -186,6 +191,9 @@
		#define VIG_CSC_10_EN BIT(0)
		#define CSC_10BIT_OFFSET 4

		/* traffic shaper clock in Hz */
		#define TS_CLK 19200000

		static inline int _sspp_subblk_offset(struct sde_hw_pipe *ctx,
		int s_id,
		u32 *idx)
		@@ -1041,6 +1049,51 @@ static void sde_hw_sspp_get_sbuf_status(struct sde_hw_pipe *ctx,
		status->rd_ptr[1] = val & 0xffff;
		}

		static void sde_hw_sspp_setup_ts_prefill(struct sde_hw_pipe *ctx,
		struct sde_hw_pipe_ts_cfg *cfg,
		enum sde_sspp_multirect_index index)
		{
		u32 idx;
		u32 ts_offset, ts_prefill_offset;
		u32 ts_count = 0, ts_bytes = 0;
		const struct sde_sspp_cfg *cap;

		if (!ctx \|\| !cfg \|\| !ctx->cap)
		return;

		if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx))
		return;

		cap = ctx->cap;

		if (index == SDE_SSPP_RECT_0 &&
		test_bit(SDE_SSPP_TS_PREFILL, &cap->features)) {
		ts_offset = SSPP_TRAFFIC_SHAPER;
		ts_prefill_offset = SSPP_TRAFFIC_SHAPER_PREFILL;
		} else if (index == SDE_SSPP_RECT_1 &&
		test_bit(SDE_SSPP_TS_PREFILL_REC1, &cap->features)) {
		ts_offset = SSPP_TRAFFIC_SHAPER_REC1;
		ts_prefill_offset = SSPP_TRAFFIC_SHAPER_REC1_PREFILL;
		} else {
		return;
		}

		if (cfg->time) {
		ts_bytes = mult_frac(TS_CLK * 1000000ULL, cfg->size,
		cfg->time);
		if (ts_bytes > SSPP_TRAFFIC_SHAPER_BPC_MAX)
		ts_bytes = SSPP_TRAFFIC_SHAPER_BPC_MAX;
		}

		if (ts_bytes) {
		ts_count = DIV_ROUND_UP_ULL(cfg->size, ts_bytes);
		ts_bytes \|= BIT(31) \| BIT(27);
		}

		SDE_REG_WRITE(&ctx->hw, ts_offset, ts_bytes);
		SDE_REG_WRITE(&ctx->hw, ts_prefill_offset, ts_count);
		}

		static void _setup_layer_ops(struct sde_hw_pipe *c,
		unsigned long features)
		{
		@@ -1062,6 +1115,9 @@ static void _setup_layer_ops(struct sde_hw_pipe *c,
		c->ops.setup_qos_ctrl = sde_hw_sspp_setup_qos_ctrl;
		}

		if (test_bit(SDE_SSPP_TS_PREFILL, &features))
		c->ops.setup_ts_prefill = sde_hw_sspp_setup_ts_prefill;

		if (test_bit(SDE_SSPP_CSC, &features) \|\|
		test_bit(SDE_SSPP_CSC_10BIT, &features))
		c->ops.setup_csc = sde_hw_sspp_setup_csc;

drivers/gpu/drm/msm/sde/sde_hw_sspp.h

+20 −0

Original line number	Diff line number	Diff line
		@@ -342,6 +342,16 @@ struct sde_hw_pipe_sc_cfg {
		u32 rd_op_type;
		};

		/**
		* struct sde_hw_pipe_ts_cfg - traffic shaper configuration
		* @size: size to prefill in bytes, or zero to disable
		* @time: time to prefill in usec, or zero to disable
		*/
		struct sde_hw_pipe_ts_cfg {
		u64 size;
		u64 time;
		};

		/**
		* Maximum number of stream buffer plane
		*/
		@@ -554,6 +564,16 @@ struct sde_hw_sspp_ops {
		*/
		void (get_sbuf_status)(struct sde_hw_pipe ctx,
		struct sde_hw_pipe_sbuf_status *status);

		/**
		* setup_ts_prefill - setup prefill traffic shaper
		* @ctx: Pointer to pipe context
		* @cfg: Pointer to traffic shaper configuration
		* @index: rectangle index in multirect
		*/
		void (setup_ts_prefill)(struct sde_hw_pipe ctx,
		struct sde_hw_pipe_ts_cfg *cfg,
		enum sde_sspp_multirect_index index);
		};

		/**