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Commit d0ed9c46 authored by Padmanabhan Komanduru's avatar Padmanabhan Komanduru Committed by Gerrit - the friendly Code Review server
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drm: msm: dp: add support to retrieve the sink BPP from EDID data 



The bits per pixel programmed to the DP controller needs to be based
on the sink capabilities. Add changes to retrieve this BPP value
from the EDID information.

Change-Id: Ic94afdbe82770b149523431e66bc4919c87e5c29
Signed-off-by: default avatarPadmanabhan Komanduru <pkomandu@codeaurora.org>
parent d84b38b2

drivers/gpu/drm/msm/dp/dp_drm.c

+6 −3
Original line number Diff line number Diff line
@@ -26,8 +26,10 @@ 
#define to_dp_bridge(x)     container_of((x), struct dp_bridge, base)



static void convert_to_dp_mode(const struct drm_display_mode *drm_mode,

				struct dp_display_mode *dp_mode)

			struct dp_display_mode *dp_mode, struct dp_display *dp)

{

	const u32 num_components = 3;



	memset(dp_mode, 0, sizeof(*dp_mode));



	dp_mode->timing.h_active = drm_mode->hdisplay;
@@ -45,6 +47,7 @@ static void convert_to_dp_mode(const struct drm_display_mode *drm_mode, 


	dp_mode->timing.v_front_porch = drm_mode->vsync_start -

					 drm_mode->vdisplay;

	dp_mode->timing.bpp = dp->connector->display_info.bpc * num_components;



	dp_mode->timing.refresh_rate = drm_mode->vrefresh;
@@ -235,7 +238,7 @@ static void dp_bridge_mode_set(struct drm_bridge *drm_bridge, 
	dp = bridge->display;



	memset(&bridge->dp_mode, 0x0, sizeof(struct dp_display_mode));

	convert_to_dp_mode(adjusted_mode, &bridge->dp_mode);

	convert_to_dp_mode(adjusted_mode, &bridge->dp_mode, dp);

}



static bool dp_bridge_mode_fixup(struct drm_bridge *drm_bridge,
@@ -257,7 +260,7 @@ static bool dp_bridge_mode_fixup(struct drm_bridge *drm_bridge, 
	bridge = to_dp_bridge(drm_bridge);

	dp = bridge->display;



	convert_to_dp_mode(mode, &dp_mode);

	convert_to_dp_mode(mode, &dp_mode, dp);



	rc = dp->validate_mode(dp, &dp_mode);

	if (rc) {

drivers/gpu/drm/msm/dp/dp_panel.c

+0 −2
Original line number Diff line number Diff line
@@ -201,8 +201,6 @@ static u32 dp_panel_get_link_rate(struct dp_panel *dp_panel) 
	max_rate = drm_dp_link_rate_to_bw_code(dp_panel->dp_link.rate);

	pinfo = &dp_panel->pinfo;



	pinfo->bpp = 24;



	/*

	 * The max pixel clock supported is 675Mhz. The

	 * current calculations below will make sure