Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit d0b6342d authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge branch 'fixes' into next/multiplatform 

The 'fixes' branch contains d5d4fdd8 ("irqchip/versatile-fpga:
Fix PCI IRQ mapping on Versatile PB") that is required for booting
the versatile platform prior to the rework in this branch, but
including both causes a build-time error.

I'm doing an evil merge here to pull in the fixes branch so we have
that commit included but at the same time revert the trivial change.
This gives us a bisectable history.

* fixes: (22 commits)
  fsl-ifc: add missing include on ARM64
  ls2080a/dts: Add little endian property for GPIO IP block
  dt-bindings: define little-endian property for QorIQ GPIO
  ARM64: dts: ls2080a: fix eSDHC endianness
  ARM: dts: vf610: use reset values for L2 cache latencies
  ARM: pxa: use PWM lookup table for all machines
  ARM: dts: berlin: add 2nd clock for BG2Q sdhci0 and sdhci1
  ARM: dts: berlin: correct BG2Q's sdhci2 2nd clock
  ARM: dts: am4372: fix clock source for arm twd and global timers
  ARM: at91: fix pinctrl driver selection
  ARM: at91/dt: add always-on to 1.8V regulator
  ARM: dts: vf610: fix clock definition for SAI2
  ARM: imx: clk-vf610: fix SAI clock tree
  ARM: ixp4xx: fix read{b,w,l} return types
  irqchip/versatile-fpga: Fix PCI IRQ mapping on Versatile PB
  ARM: OMAP2+: enable REGULATOR_FIXED_VOLTAGE
  ARM: dts: add dm816x missing spi DT dma handles
  ARM: dts: add dm816x missing #mbox-cells
  cpufreq: s3c24xx: Do not mark s3c2410_plls_add as __init
  bus: sunxi-rsb: unlock on error in sunxi_rsb_read()
  ...
parents 70722803 c4aa1937

Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt

+4 −0
Original line number Diff line number Diff line
@@ -11,6 +11,10 @@ Required properties: 
      0 = active high

      1 = active low



Optional properties:

- little-endian : GPIO registers are used as little endian. If not

                  present registers are used as big endian by default.



Example:



gpio0: gpio@1100 {

arch/arm/boot/dts/am4372.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -74,7 +74,7 @@ 
		reg = <0x48240200 0x100>;

		interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-parent = <&gic>;

		clocks = <&dpll_mpu_m2_ck>;

		clocks = <&mpu_periphclk>;

	};



	local_timer: timer@48240600 {
@@ -82,7 +82,7 @@ 
		reg = <0x48240600 0x100>;

		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-parent = <&gic>;

		clocks = <&dpll_mpu_m2_ck>;

		clocks = <&mpu_periphclk>;

	};



	l2-cache-controller@48242000 {

arch/arm/boot/dts/am43xx-clocks.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -259,6 +259,14 @@ 
		ti,invert-autoidle-bit;

	};



	mpu_periphclk: mpu_periphclk {

		#clock-cells = <0>;

		compatible = "fixed-factor-clock";

		clocks = <&dpll_mpu_m2_ck>;

		clock-mult = <1>;

		clock-div = <2>;

	};



	dpll_ddr_ck: dpll_ddr_ck {

		#clock-cells = <0>;

		compatible = "ti,am3-dpll-clock";

arch/arm/boot/dts/at91-sama5d2_xplained.dts

+1 −0
Original line number Diff line number Diff line
@@ -184,6 +184,7 @@ 
							regulator-name = "VDD_SDHC_1V8";

							regulator-min-microvolt = <1800000>;

							regulator-max-microvolt = <1800000>;

							regulator-always-on;

						};

					};

				};

arch/arm/boot/dts/berlin2q.dtsi

+5 −3
Original line number Diff line number Diff line
@@ -118,7 +118,8 @@ 
		sdhci0: sdhci@ab0000 {

			compatible = "mrvl,pxav3-mmc";

			reg = <0xab0000 0x200>;

			clocks = <&chip_clk CLKID_SDIO1XIN>;

			clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>;

			clock-names = "io", "core";

			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;

			status = "disabled";

		};
@@ -126,7 +127,8 @@ 
		sdhci1: sdhci@ab0800 {

			compatible = "mrvl,pxav3-mmc";

			reg = <0xab0800 0x200>;

			clocks = <&chip_clk CLKID_SDIO1XIN>;

			clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>;

			clock-names = "io", "core";

			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;

			status = "disabled";

		};
@@ -135,7 +137,7 @@ 
			compatible = "mrvl,pxav3-mmc";

			reg = <0xab1000 0x200>;

			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_NFC>;

			clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_SDIO>;

			clock-names = "io", "core";

			status = "disabled";

		};