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Commit d0a8ecde authored by Laxminath Kasam's avatar Laxminath Kasam
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asoc: codecs: sdm660_cdc: Return from digclock control if cacheonly 



While SSR in progress, and teardown of session happens
it will request for afe clock enable continuously at
digclock control. Return from digclock control
if cache only mode is set which avoids continuous
afe failures and watchdog bite failure at stability runs.

Change-Id: I9a2349c1e937fc7606c760afa17b1eb0d4833126
Signed-off-by: default avatarLaxminath Kasam <lkasam@codeaurora.org>
parent 61567eef

asoc/codecs/sdm660_cdc/msm-digital-cdc.c

+2 −2
Original line number Diff line number Diff line
@@ -122,6 +122,8 @@ static int msm_digcdc_clock_control(bool flag) 
	if (flag) {

		mutex_lock(&pdata->cdc_int_mclk0_mutex);

		if (atomic_read(&pdata->int_mclk0_enabled) == false) {

			if (msm_dig_cdc->regmap->cache_only == true)

				return ret;

			if (pdata->native_clk_set)

				pdata->digital_cdc_core_clk.clk_freq_in_hz =

							NATIVE_MCLK_RATE;
@@ -141,8 +143,6 @@ static int msm_digcdc_clock_control(bool flag) 
				 */

				msm_dig_cdc->regmap->cache_only = true;

				return ret;

			} else {

				msm_dig_cdc->regmap->cache_only = false;

			}

			pr_debug("enabled digital codec core clk\n");

			atomic_set(&pdata->int_mclk0_enabled, true);