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Commit d0a31245 authored by Aditya Bavanari's avatar Aditya Bavanari Committed by Banajit Goswami
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ASoC: sdm660_cdc: Update volatile register set for cache bypass 



Update the volatile register set for cache bypassing. Set
only required registers as volatile and others as
non volatile in order to enable register read from
cache.

CRs-Fixed: 2031818
Change-Id: Ib53798a3f81fc133f6f3902f7bac750cca1cabc6
Signed-off-by: default avatarAditya Bavanari <abavanar@codeaurora.org>
parent 3fa8397e
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