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Commit d02440be authored by Clarence Ip's avatar Clarence Ip
Browse files

drm/msm/sde: set bus attributes correctly for inline rotatation 



Update the allocate/no-allocation setting for the inline
rotation and normal use cases and specify the appropriate
hint to the SMMU to respect those settings during the
buffer mapping.

CRs-Fixed: 2048692
Change-Id: I6a0238dc0055674df18c98bede1870226781748c
Signed-off-by: default avatarClarence Ip <cip@codeaurora.org>
parent 24b7c36c

drivers/gpu/drm/msm/sde/sde_kms.c

+12 −1
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ 


#include "msm_drv.h"

#include "msm_mmu.h"

#include "msm_gem.h"



#include "dsi_display.h"

#include "dsi_drm.h"
@@ -950,6 +951,13 @@ static void sde_kms_fbo_destroy(struct sde_kms_fbo *fbo) 
	}

}



static void sde_kms_set_gem_flags(struct msm_gem_object *msm_obj,

		uint32_t flags)

{

	if (msm_obj)

		msm_obj->flags |= flags;

}



struct sde_kms_fbo *sde_kms_fbo_alloc(struct drm_device *dev, u32 width,

		u32 height, u32 pixel_format, u64 modifier[4], u32 flags)

{
@@ -1036,10 +1044,13 @@ struct sde_kms_fbo *sde_kms_fbo_alloc(struct drm_device *dev, u32 width, 
			fbo->bo[0] = NULL;

			goto done;

		}



		/* insert extra bo flags */

		sde_kms_set_gem_flags(to_msm_bo(fbo->bo[0]), MSM_BO_KEEPATTRS);

	} else {

		mutex_lock(&dev->struct_mutex);

		fbo->bo[0] = msm_gem_new(dev, fbo->layout.total_size,

				MSM_BO_SCANOUT | MSM_BO_WC);

				MSM_BO_SCANOUT | MSM_BO_WC | MSM_BO_KEEPATTRS);

		if (IS_ERR(fbo->bo[0])) {

			mutex_unlock(&dev->struct_mutex);

			SDE_ERROR("failed to new gem buffer\n");

drivers/gpu/drm/msm/sde/sde_plane.c

+1 −1
Original line number Diff line number Diff line
@@ -3007,7 +3007,7 @@ static int sde_plane_sspp_atomic_update(struct drm_plane *plane, 
						SDE_PIPE_SC_OP_MODE_OFFLINE;

				pstate->sc_cfg.rd_en = false;

				pstate->sc_cfg.rd_scid = 0;

				pstate->sc_cfg.rd_noallocate = false;

				pstate->sc_cfg.rd_noallocate = true;

				pstate->sc_cfg.rd_op_type =

					SDE_PIPE_SC_RD_OP_TYPE_CACHEABLE;

			}