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Commit d012b4de authored by Deepak Katragadda's avatar Deepak Katragadda
Browse files

clk: qcom: Enable the GPLL0 inputs to DISP and GPU CCs when needed 



Currently, the gpll0 input to display and graphics clock
controllers are not enabled when needed. Correct this
behavior.

Change-Id: I6d5b1e2c0b38e810bb481f05ed4663250ef82030
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent b0201565

drivers/clk/qcom/dispcc-sdm845.c

+2 −2
Original line number Diff line number Diff line
@@ -106,8 +106,8 @@ static const struct parent_map disp_cc_parent_map_3[] = { 
static const char * const disp_cc_parent_names_3[] = {

	"bi_tcxo",

	"disp_cc_pll0",

	"gpll0",

	"gpll0",

	"gcc_disp_gpll0_clk_src",

	"gcc_disp_gpll0_div_clk_src",

	"core_bi_pll_test_se",

};

drivers/clk/qcom/gpucc-sdm845.c

+5 −5
Original line number Diff line number Diff line
@@ -80,8 +80,8 @@ static const char * const gpu_cc_parent_names_0[] = { 
	"bi_tcxo",

	"gpu_cc_pll0",

	"gpu_cc_pll1",

	"gpll0",

	"gpll0_out_even",

	"gcc_gpu_gpll0_clk_src",

	"gcc_gpu_gpll0_div_clk_src",

	"core_bi_pll_test_se",

};
@@ -101,7 +101,7 @@ static const char * const gpu_cc_parent_names_1[] = { 
	"gpu_cc_pll0_out_odd",

	"gpu_cc_pll1_out_even",

	"gpu_cc_pll1_out_odd",

	"gpll0",

	"gcc_gpu_gpll0_clk_src",

	"core_bi_pll_test_se",

};
@@ -114,8 +114,8 @@ static const struct parent_map gpu_cc_parent_map_2[] = { 


static const char * const gpu_cc_parent_names_2[] = {

	"bi_tcxo",

	"gpll0",

	"gpll0",

	"gcc_gpu_gpll0_clk_src",

	"gcc_gpu_gpll0_div_clk_src",

	"core_bi_pll_test_se",

};