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Commit d009b1d3 authored by Benet Clark's avatar Benet Clark Committed by Narendra Muppalla
Browse files

drm/msm/sde: Add support for Memory Color in plane 



Add support for skin, sky, and foliage memory color hardware in
planes which have color processing hardwares.

Change-Id: I9ec72f44f36939cae90215bc668f3186d140e8b8
Signed-off-by: default avatarBenet Clark <benetc@codeaurora.org>
parent eb1b446c

drivers/gpu/drm/msm/msm_drv.h

+3 −0
Original line number Diff line number Diff line
@@ -84,6 +84,9 @@ enum msm_mdp_plane_property { 
	PLANE_PROP_SCALER_LUT_ED,

	PLANE_PROP_SCALER_LUT_CIR,

	PLANE_PROP_SCALER_LUT_SEP,

	PLANE_PROP_SKIN_COLOR,

	PLANE_PROP_SKY_COLOR,

	PLANE_PROP_FOLIAGE_COLOR,



	/* # of blob properties */

	PLANE_PROP_BLOBCOUNT,

drivers/gpu/drm/msm/sde/sde_color_processing.h

+12 −1
Original line number Diff line number Diff line 


/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify
@@ -16,6 +15,18 @@ 
#define _SDE_COLOR_PROCESSING_H

#include <drm/drm_crtc.h>



/*

 * PA MEMORY COLOR types

 * @MEMCOLOR_SKIN          Skin memory color type

 * @MEMCOLOR_SKY           Sky memory color type

 * @MEMCOLOR_FOLIAGE       Foliage memory color type

 */

enum sde_memcolor_type {

	MEMCOLOR_SKIN = 0,

	MEMCOLOR_SKY,

	MEMCOLOR_FOLIAGE

};



/**

 * sde_cp_crtc_init(): Initialize color processing lists for a crtc.

 *                     Should be called during crtc initialization.

drivers/gpu/drm/msm/sde/sde_hw_color_processing_v1_7.c

+81 −0
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ 
 * GNU General Public License for more details.

 */



#include <drm/msm_drm_pp.h>

#include "sde_hw_color_processing_v1_7.h"



#define PA_HUE_OFF		0x110
@@ -21,6 +22,23 @@ 
#define PA_CONT_OFF		0x11C

#define PA_CONT_MASK		0xFF



#define MEMCOL_PWL0_OFF		0x88

#define MEMCOL_PWL0_MASK	0xFFFF07FF

#define MEMCOL_PWL1_OFF		0x8C

#define MEMCOL_PWL1_MASK	0xFFFFFFFF

#define MEMCOL_HUE_REGION_OFF	0x90

#define MEMCOL_HUE_REGION_MASK	0x7FF07FF

#define MEMCOL_SAT_REGION_OFF	0x94

#define MEMCOL_SAT_REGION_MASK	0xFFFFFF

#define MEMCOL_VAL_REGION_OFF	0x98

#define MEMCOL_VAL_REGION_MASK	0xFFFFFF

#define MEMCOL_P0_LEN		0x14

#define MEMCOL_P1_LEN		0x8

#define MEMCOL_PWL2_OFF		0x218

#define MEMCOL_PWL2_MASK	0xFFFFFFFF

#define MEMCOL_BLEND_GAIN_OFF	0x21C

#define MEMCOL_PWL_HOLD_OFF	0x214



#define VIG_OP_PA_EN		BIT(4)

#define VIG_OP_PA_SKIN_EN	BIT(5)

#define VIG_OP_PA_FOL_EN	BIT(6)
@@ -119,3 +137,66 @@ void sde_setup_pipe_pa_cont_v1_7(struct sde_hw_pipe *ctx, void *cfg) 


	SDE_REG_WRITE(&ctx->hw, base, opmode);

}



void sde_setup_pipe_pa_memcol_v1_7(struct sde_hw_pipe *ctx,

				   enum sde_memcolor_type type,

				   void *cfg)

{

	struct drm_msm_memcol *mc = cfg;

	u32 base = ctx->cap->sblk->memcolor_blk.base;

	u32 off, op, mc_en, hold = 0;

	u32 mc_i = 0;



	switch (type) {

	case MEMCOLOR_SKIN:

		mc_en = VIG_OP_PA_SKIN_EN;

		mc_i = 0;

		break;

	case MEMCOLOR_SKY:

		mc_en = VIG_OP_PA_SKY_EN;

		mc_i = 1;

		break;

	case MEMCOLOR_FOLIAGE:

		mc_en = VIG_OP_PA_FOL_EN;

		mc_i = 2;

		break;

	default:

		DRM_ERROR("Invalid memory color type %d\n", type);

		return;

	}



	op = SDE_REG_READ(&ctx->hw, base);

	if (!mc) {

		op &= ~mc_en;

		if (PA_DISABLE_REQUIRED(op))

			op &= ~VIG_OP_PA_EN;

		SDE_REG_WRITE(&ctx->hw, base, op);

		return;

	}



	off = base + (mc_i * MEMCOL_P0_LEN);

	SDE_REG_WRITE(&ctx->hw, (off + MEMCOL_PWL0_OFF),

		      mc->color_adjust_p0 & MEMCOL_PWL0_MASK);

	SDE_REG_WRITE(&ctx->hw, (off + MEMCOL_PWL1_OFF),

		      mc->color_adjust_p1 & MEMCOL_PWL1_MASK);

	SDE_REG_WRITE(&ctx->hw, (off + MEMCOL_HUE_REGION_OFF),

		      mc->hue_region & MEMCOL_HUE_REGION_MASK);

	SDE_REG_WRITE(&ctx->hw, (off + MEMCOL_SAT_REGION_OFF),

		      mc->sat_region & MEMCOL_SAT_REGION_MASK);

	SDE_REG_WRITE(&ctx->hw, (off + MEMCOL_VAL_REGION_OFF),

		      mc->val_region & MEMCOL_VAL_REGION_MASK);



	off = base + (mc_i * MEMCOL_P1_LEN);

	SDE_REG_WRITE(&ctx->hw, (off + MEMCOL_PWL2_OFF),

		      mc->color_adjust_p2 & MEMCOL_PWL2_MASK);

	SDE_REG_WRITE(&ctx->hw, (off + MEMCOL_BLEND_GAIN_OFF), mc->blend_gain);



	hold = SDE_REG_READ(&ctx->hw, off + MEMCOL_PWL_HOLD_OFF);

	hold &= ~(0xF << (mc_i * 4));

	hold |= ((mc->sat_hold & 0x3) << (mc_i * 4));

	hold |= ((mc->val_hold & 0x3) << ((mc_i * 4) + 2));

	SDE_REG_WRITE(&ctx->hw, (off + MEMCOL_PWL_HOLD_OFF), hold);



	op |= VIG_OP_PA_EN | mc_en;

	SDE_REG_WRITE(&ctx->hw, base, op);

}

drivers/gpu/drm/msm/sde/sde_hw_color_processing_v1_7.h

+10 −0
Original line number Diff line number Diff line
@@ -43,4 +43,14 @@ void sde_setup_pipe_pa_val_v1_7(struct sde_hw_pipe *ctx, void *cfg); 
 */

void sde_setup_pipe_pa_cont_v1_7(struct sde_hw_pipe *ctx, void *cfg);



/**

 * sde_setup_pipe_pa_memcol_v1_7 - setup SSPP memory color in v1.7 hardware

 * @ctx: Pointer to pipe context

 * @type: Memory color type (Skin, sky, or foliage)

 * @cfg: Pointer to memory color config data

 */

void sde_setup_pipe_pa_memcol_v1_7(struct sde_hw_pipe *ctx,

				   enum sde_memcolor_type type,

				   void *cfg);



#endif

drivers/gpu/drm/msm/sde/sde_hw_sspp.c

+7 −0
Original line number Diff line number Diff line
@@ -879,6 +879,13 @@ static void _setup_layer_ops(struct sde_hw_pipe *c, 
			c->ops.setup_pa_cont = sde_setup_pipe_pa_cont_v1_7;

		}

	}



	if (test_bit(SDE_SSPP_MEMCOLOR, &features)) {

		if (c->cap->sblk->memcolor_blk.version ==

			(SDE_COLOR_PROCESS_VER(0x1, 0x7)))

			c->ops.setup_pa_memcolor =

				sde_setup_pipe_pa_memcol_v1_7;

	}

}



static struct sde_sspp_cfg *_sspp_offset(enum sde_sspp sspp,