Loading arch/arm64/boot/dts/qcom/msm8953-qrd.dtsi +26 −1 Original line number Diff line number Diff line Loading @@ -16,7 +16,32 @@ &soc { i2c@78b7000 { /* BLSP1 QUP3 */ /delete-node/ synaptics@4b; status = "okay"; synaptics@4b { compatible = "synaptics,dsx-i2c"; reg = <0x4b>; interrupt-parent = <&tlmm>; interrupts = <65 0x2008>; vdd_ana-supply = <&vdd_vreg>; vcc_i2c-supply = <&pm8953_l6>; synaptics,pwr-reg-name = "vdd_ana"; synaptics,bus-reg-name = "vcc_i2c"; synaptics,irq-gpio = <&tlmm 65 0x2008>; synaptics,irq-on-state = <0>; synaptics,irq-flags = <0x2008>; synaptics,power-delay-ms = <200>; synaptics,reset-delay-ms = <200>; synaptics,max-y-for-2d = <1919>; synaptics,cap-button-codes = <139 158 172>; synaptics,vir-button-codes = <139 180 2000 320 160 158 540 2000 320 160 172 900 2000 320 160>; synaptics,resume-in-workqueue; /* Underlying clocks used by secure touch */ clock-names = "iface_clk", "core_clk"; clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, <&clock_gcc clk_gcc_blsp1_qup3_i2c_apps_clk>; }; }; vdd_vreg: vdd_vreg { Loading Loading
arch/arm64/boot/dts/qcom/msm8953-qrd.dtsi +26 −1 Original line number Diff line number Diff line Loading @@ -16,7 +16,32 @@ &soc { i2c@78b7000 { /* BLSP1 QUP3 */ /delete-node/ synaptics@4b; status = "okay"; synaptics@4b { compatible = "synaptics,dsx-i2c"; reg = <0x4b>; interrupt-parent = <&tlmm>; interrupts = <65 0x2008>; vdd_ana-supply = <&vdd_vreg>; vcc_i2c-supply = <&pm8953_l6>; synaptics,pwr-reg-name = "vdd_ana"; synaptics,bus-reg-name = "vcc_i2c"; synaptics,irq-gpio = <&tlmm 65 0x2008>; synaptics,irq-on-state = <0>; synaptics,irq-flags = <0x2008>; synaptics,power-delay-ms = <200>; synaptics,reset-delay-ms = <200>; synaptics,max-y-for-2d = <1919>; synaptics,cap-button-codes = <139 158 172>; synaptics,vir-button-codes = <139 180 2000 320 160 158 540 2000 320 160 172 900 2000 320 160>; synaptics,resume-in-workqueue; /* Underlying clocks used by secure touch */ clock-names = "iface_clk", "core_clk"; clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, <&clock_gcc clk_gcc_blsp1_qup3_i2c_apps_clk>; }; }; vdd_vreg: vdd_vreg { Loading