Loading drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c +7 −1 Original line number Diff line number Diff line Loading @@ -404,6 +404,7 @@ static void sde_encoder_phys_vid_vblank_irq(void *arg, int irq_idx) struct sde_hw_ctl *hw_ctl; unsigned long lock_flags; u32 flush_register = 0; u32 reset_status = 0; int new_cnt = -1, old_cnt = -1; u32 event = 0; Loading Loading @@ -446,10 +447,15 @@ static void sde_encoder_phys_vid_vblank_irq(void *arg, int irq_idx) if (flush_register == 0) new_cnt = atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0); if (hw_ctl && hw_ctl->ops.get_reset) reset_status = hw_ctl->ops.get_reset(hw_ctl); spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); SDE_EVT32_IRQ(DRMID(phys_enc->parent), vid_enc->hw_intf->idx - INTF_0, old_cnt, new_cnt, flush_register, event); old_cnt, new_cnt, reset_status ? SDE_EVTLOG_ERROR : 0, flush_register, event); /* Signal any waiting atomic commit thread */ wake_up_all(&phys_enc->pending_kickoff_wq); Loading drivers/gpu/drm/msm/sde/sde_hw_ctl.c +8 −0 Original line number Diff line number Diff line Loading @@ -347,6 +347,13 @@ static u32 sde_hw_ctl_poll_reset_status(struct sde_hw_ctl *ctx, u32 timeout_us) return status; } static u32 sde_hw_ctl_get_reset_status(struct sde_hw_ctl *ctx) { if (!ctx) return 0; return (u32)SDE_REG_READ(&ctx->hw, CTL_SW_RESET); } static int sde_hw_ctl_reset_control(struct sde_hw_ctl *ctx) { struct sde_hw_blk_reg_map *c = &ctx->hw; Loading Loading @@ -632,6 +639,7 @@ static void _setup_ctl_ops(struct sde_hw_ctl_ops *ops, ops->read_ctl_layers = sde_hw_ctl_read_ctl_layers; ops->setup_intf_cfg = sde_hw_ctl_intf_cfg; ops->reset = sde_hw_ctl_reset_control; ops->get_reset = sde_hw_ctl_get_reset_status; ops->hard_reset = sde_hw_ctl_hard_reset; ops->wait_reset_status = sde_hw_ctl_wait_reset_status; ops->clear_all_blendstages = sde_hw_ctl_clear_all_blendstages; Loading drivers/gpu/drm/msm/sde/sde_hw_ctl.h +7 −0 Original line number Diff line number Diff line Loading @@ -152,6 +152,13 @@ struct sde_hw_ctl_ops { int (*reset)(struct sde_hw_ctl *c); /** * get_reset - check ctl reset status bit * @ctx : ctl path ctx pointer * Returns: current value of ctl reset status */ u32 (*get_reset)(struct sde_hw_ctl *ctx); /** * hard_reset - force reset on ctl_path * @ctx : ctl path ctx pointer Loading Loading
drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c +7 −1 Original line number Diff line number Diff line Loading @@ -404,6 +404,7 @@ static void sde_encoder_phys_vid_vblank_irq(void *arg, int irq_idx) struct sde_hw_ctl *hw_ctl; unsigned long lock_flags; u32 flush_register = 0; u32 reset_status = 0; int new_cnt = -1, old_cnt = -1; u32 event = 0; Loading Loading @@ -446,10 +447,15 @@ static void sde_encoder_phys_vid_vblank_irq(void *arg, int irq_idx) if (flush_register == 0) new_cnt = atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0); if (hw_ctl && hw_ctl->ops.get_reset) reset_status = hw_ctl->ops.get_reset(hw_ctl); spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); SDE_EVT32_IRQ(DRMID(phys_enc->parent), vid_enc->hw_intf->idx - INTF_0, old_cnt, new_cnt, flush_register, event); old_cnt, new_cnt, reset_status ? SDE_EVTLOG_ERROR : 0, flush_register, event); /* Signal any waiting atomic commit thread */ wake_up_all(&phys_enc->pending_kickoff_wq); Loading
drivers/gpu/drm/msm/sde/sde_hw_ctl.c +8 −0 Original line number Diff line number Diff line Loading @@ -347,6 +347,13 @@ static u32 sde_hw_ctl_poll_reset_status(struct sde_hw_ctl *ctx, u32 timeout_us) return status; } static u32 sde_hw_ctl_get_reset_status(struct sde_hw_ctl *ctx) { if (!ctx) return 0; return (u32)SDE_REG_READ(&ctx->hw, CTL_SW_RESET); } static int sde_hw_ctl_reset_control(struct sde_hw_ctl *ctx) { struct sde_hw_blk_reg_map *c = &ctx->hw; Loading Loading @@ -632,6 +639,7 @@ static void _setup_ctl_ops(struct sde_hw_ctl_ops *ops, ops->read_ctl_layers = sde_hw_ctl_read_ctl_layers; ops->setup_intf_cfg = sde_hw_ctl_intf_cfg; ops->reset = sde_hw_ctl_reset_control; ops->get_reset = sde_hw_ctl_get_reset_status; ops->hard_reset = sde_hw_ctl_hard_reset; ops->wait_reset_status = sde_hw_ctl_wait_reset_status; ops->clear_all_blendstages = sde_hw_ctl_clear_all_blendstages; Loading
drivers/gpu/drm/msm/sde/sde_hw_ctl.h +7 −0 Original line number Diff line number Diff line Loading @@ -152,6 +152,13 @@ struct sde_hw_ctl_ops { int (*reset)(struct sde_hw_ctl *c); /** * get_reset - check ctl reset status bit * @ctx : ctl path ctx pointer * Returns: current value of ctl reset status */ u32 (*get_reset)(struct sde_hw_ctl *ctx); /** * hard_reset - force reset on ctl_path * @ctx : ctl path ctx pointer Loading